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gpu: s6 gpu bringup [1/1]

Browse Source 
PD#SWPL-156542

Problem:
s6 gpu bringup

Solution:
add gpu config

Verify:
s6 pxp

Change-Id: I95346484c64d09d77064863411ca8b45da80fbc2
Signed-off-by: Yongjie Zhu <yongjie.zhu@amlogic.com>
This commit is contained in:
Yongjie Zhu
2024-01-25 02:21:49 +00:00
committed by pengzhao.liu
parent a078845dfb
commit 1db27e26bb
2 changed files with 56 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-s6.dtsi
+47 -37
View File
@@ -21,7 +21,7 @@
#include <dt-bindings/mailbox/amlogic,mbox.h>
#include <dt-bindings/mailbox/s6-mbox.h>
#include "meson-ir-map.dtsi"
#include "mesong12a-bifrost.dtsi"
#include "meson-valhall.dtsi"
/ {
cpus:cpus {
#address-cells = <2>;
@@ -2316,6 +2316,14 @@
chosen {
bootargs = "usbcore.autosuspend=-1";
};
gpu_opp_table: gpu_opp_table {
compatible = "operating-points-v2";
opp-400 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150>;
};
};
};
&periphs_pinctrl {
@@ -3011,55 +3019,57 @@
function = "spdif_in";
};
};
gpu_protected_memory_allocator: protected-memory-allocator {
compatible = "arm,protected-memory-allocator";
memory-region = <&mali_protected>;
};
};
&gpu{
reg = <0x0 0xFE400000 0x0 0x04000>, /*mali APB bus base address*/
status = "okay";
operating-points-v2 = <&gpu_opp_table>;
reg = <0x0 0xFD000000 0x0 0x800000>, /*mali APB bus base address*/
<0x0 0xFE002000 0x0 0x01000>, /*reset register*/
<0x0 0xFF800000 0x0 0x01000>, /*aobus TODO update*/
<0x0 0xFF63c000 0x0 0x01000>, /*hiubus for clk cntl*/
<0x0 0xFE002000 0x0 0x01000>; /*reset register*/
<0x0 0xFF000000 0x0 0x01000>; /*aobus TODO update*/
interrupts = <0 144 4>, <0 145 4>, <0 146 4>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "GPU", "MMU", "JOB";
clk_cntl_reg = <0x57>;
//clocks = <&clkc CLKID_MALI>;
//clock-names = "gpu_mux";
protected-memory-allocator = <&gpu_protected_memory_allocator>;
num_of_pp = <1>;
system-coherency = <31>;
clocks = <&clkc CLKID_MALI>,
<&clkc CLKID_MALI_STACK>;
clock-names = "gpu_mux", "gpu_stack";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
//assigned-clocks = <&clkc CLKID_GP1_PLL>,
// <&clkc CLKID_MALI_0_MUX>,
// <&clkc CLKID_MALI_0>,
// <&clkc CLKID_MALI>; /* Glitch free mux */
//assigned-clock-parents = <0>, /* Do Nothing */
// <&clkc CLKID_FCLK_DIV4>,
// <0>, /* Do Nothing */
// <&clkc CLKID_MALI_0>;
//assigned-clock-rates = <852000000>,
// <0>, /* Do Nothing */
// <500000000>,
// <0>; /* Do Nothing */
assigned-clocks = <&clkc CLKID_MALI_0_MUX>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>,
<&clkc CLKID_MALI_STACK_0_MUX>,
<&clkc CLKID_MALI_STACK_0>,
<&clkc CLKID_MALI_STACK>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV5>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>,
<&clkc CLKID_FCLK_DIV5>,
<0>,
<&clkc CLKID_MALI_STACK_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<400000000>,
<0>,
<0>,
<400000000>,
<0>; /* Do Nothing */
tbl = <&dvfs285_cfg
&dvfs400_cfg
&dvfs500_cfg
&dvfs666_cfg
&dvfs850_cfg
&dvfs850_cfg>;
dvfs850_cfg:dvfs850_cfg {
clk_freq = <852000000>;
clk_parent = "gp1_pll";
clkp_freq = <852000000>;
clk_reg = <0x200>;
voltage = <1150>;
keep_count = <5>;
threshold = <80 255>;
};
tbl = <&dvfs400_cfg>;//bringup s6 use fix clock 400M
};
arch/arm64/boot/dts/amlogic/s6_pxp.dts
+9
View File
@@ -112,6 +112,15 @@
size = <0x0 0x0>;
alignment = <0x0 0x400000>;
};
mali_protected: mali_protected@c0000000 {
compatible = "mali-reserved";
no-map;
/* 16M with high version than valhall-r41p0,
* 64M with low version than valhall-r41p0
*/
size = <0x0 0x0>;
alignment = <0x0 0x400000>;
};
/*di CMA pool */
di_cma_reserved:linux,di_cma {
compatible = "shared-dma-pool";