shinys000114/kernel_common_drivers
1
0
Fork 0
mirror of https://github.com/hardkernel/kernel_common_drivers.git synced 2026-06-25 12:03:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

hdmirx: kernel-5.15 T5W bringup [1/1]

Browse Source 
PD#SWPL-113304

Problem:
T5W bringup

Solution:
T5W bringup

Verify:
t5w

Change-Id: I81d7be0dc515a91d4536ac37e7fb14171db426ed
Signed-off-by: Gaowei Zhao <gaowei.zhao@amlogic.com>
This commit is contained in:
Gaowei Zhao
2023-02-28 16:54:49 +08:00
committed by gerrit autosubmit
parent 299b454066
commit 2e3e628334
21 changed files with 961 additions and 426 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+132 -80
View File
@@ -91,8 +91,8 @@ struct delayed_work esm_dwork;
struct workqueue_struct *esm_wq;
struct delayed_work repeater_dwork;
struct workqueue_struct *repeater_wq;
struct work_struct amlphy_dwork;
struct workqueue_struct *amlphy_wq;
struct work_struct aml_phy_dwork;
struct workqueue_struct *aml_phy_wq;
struct work_struct clkmsr_dwork;
struct workqueue_struct *clkmsr_wq;
struct work_struct earc_hpd_dwork;
@@ -135,13 +135,13 @@ u32 en_4096_2_3840;
int en_4k_2_2k;
int en_4k_timing = 1;
int cec_dev_en;
bool dev_is_appletv_v2;
bool dev_is_apple_tv_v2;
bool hdmi_cec_en;
static bool tv_auto_power_on;
int vdin_drop_frame_cnt = 1;
/* suspend_pddq_sel:
* 0: keep phy on when suspend(don't need phy init when
* resume), it doesn't work now because phy VDDIO_3.3V
* resume), it doesn't work now because phy VDD_IO_3.3V
* will power off when suspend, and tmds clk will be low;
* 1&2: when CEC off there's no SDA low issue for MTK box,
* these workaround are not needed
@@ -386,12 +386,12 @@ static unsigned int first_bit_set(u32 data)
*/
unsigned int rx_get_bits(unsigned int data, unsigned int mask)
{
unsigned int fstbs_rtn;
unsigned int fst_bs_rtn;
unsigned int rtn_val;
fstbs_rtn = first_bit_set(mask);
if (fstbs_rtn < 32)
rtn_val = (data & mask) >> fstbs_rtn;
fst_bs_rtn = first_bit_set(mask);
if (fst_bs_rtn < 32)
rtn_val = (data & mask) >> fst_bs_rtn;
else
rtn_val = 0;
return rtn_val;
@@ -401,12 +401,12 @@ unsigned int rx_set_bits(unsigned int data,
unsigned int mask,
unsigned int value)
{
unsigned int fstbs_rtn;
unsigned int fst_bs_rtn;
unsigned int rtn_val;
fstbs_rtn = first_bit_set(mask);
if (fstbs_rtn < 32)
rtn_val = ((value << fstbs_rtn) & mask) | (data & ~mask);
fst_bs_rtn = first_bit_set(mask);
if (fst_bs_rtn < 32)
rtn_val = ((value << fst_bs_rtn) & mask) | (data & ~mask);
else
rtn_val = 0;
return rtn_val;
@@ -507,7 +507,7 @@ void hdmirx_dec_close(struct tvin_frontend_s *fe)
/*
* txl:should disable the adc ref signal for audio pll
* txlx:dont disable the adc ref signal for audio pll(not
* txlx:don't disable the adc ref signal for audio pll(not
* reset the vdac) to avoid noise issue
*/
/* For txl,also need to keep bandgap always on:SWPL-1224 */
@@ -548,7 +548,7 @@ int hdmirx_dec_isr(struct tvin_frontend_s *fe, unsigned int hcnt64)
{
struct hdmirx_dev_s *devp;
struct tvin_parm_s *parm;
u32 avmuteflag;
u32 avmute_flag;
devp = container_of(fe, struct hdmirx_dev_s, frontend);
parm = &devp->param;
@@ -556,8 +556,8 @@ int hdmirx_dec_isr(struct tvin_frontend_s *fe, unsigned int hcnt64)
if (!rx.var.force_pattern) {
/*prevent spurious pops or noise when pw down*/
if (rx.state == FSM_SIG_READY) {
avmuteflag = rx_get_avmute_sts();
if (avmuteflag == 1) {
avmute_flag = rx_get_avmute_sts();
if (avmute_flag == 1) {
rx.avmute_skip += 1;
hdmirx_set_video_mute(1);
skip_frame(2);
@@ -1052,10 +1052,53 @@ void hdmirx_get_vsi_info(struct tvin_sig_property_s *prop)
prop->trans_fmt = TVIN_TFMT_2D;
prop->dolby_vision = DV_NULL;
prop->hdr10p_info.hdr10p_on = false;
prop->cuva_info.cuva_on = false;
last_vsi_state = rx.vs_info_details.vsi_state;
}
if (rx.pre.colorspace != E_COLOR_YUV420)
prop->dolby_vision = rx.vs_info_details.dolby_vision_flag;
#ifdef MULTI_VSIF_EXPORT_TO_EMP
if (log_level & PACKET_LOG && rx.new_emp_pkt)
rx_pr("vsi_state:0x%x\n", rx.vs_info_details.vsi_state);
if (rx.vs_info_details.vsi_state & E_VSI_DV10 || rx.vs_info_details.vsi_state & E_VSI_DV15)
rx.vs_info_details.vsi_state = E_VSI_DV15;
else if (rx.vs_info_details.vsi_state & E_VSI_HDR10PLUS)
rx.vs_info_details.vsi_state = E_VSI_HDR10PLUS;
else if (rx.vs_info_details.vsi_state & E_VSI_CUVAHDR)
rx.vs_info_details.vsi_state = E_VSI_CUVAHDR;
else if (rx.vs_info_details.vsi_state & E_VSI_4K3D)
rx.vs_info_details.vsi_state = E_VSI_4K3D;
else
rx.vs_info_details.vsi_state = E_VSI_VSI21;
switch (rx.vs_info_details.vsi_state) {
case E_VSI_DV10:
case E_VSI_DV15:
prop->low_latency = rx.vs_info_details.low_latency;
if (rx.vs_info_details.dolby_vision_flag == DV_VSIF) {
memcpy(&prop->dv_vsif_raw,
&rx_pkt.multi_vs_info[DV15], 3);
memcpy((char *)(&prop->dv_vsif_raw) + 3,
&rx_pkt.multi_vs_info[DV15].PB0,
sizeof(struct tvin_dv_vsif_raw_s) - 4);
}
break;
case E_VSI_HDR10PLUS:
prop->hdr10p_info.hdr10p_on = rx.vs_info_details.hdr10plus;
memcpy(&prop->hdr10p_info.hdr10p_data, &rx_pkt.multi_vs_info[HDR10PLUS],
sizeof(struct tvin_hdr10p_data_s));
break;
case E_VSI_CUVAHDR:
prop->cuva_info.cuva_on = true;
if (rx.vs_info_details.cuva_hdr) {
memset(&prop->cuva_info.cuva_data, 0,
sizeof(struct tvin_cuva_data_s));
memcpy(&prop->cuva_info.cuva_data,
&rx_pkt.multi_vs_info[CUVAHDR], sizeof(struct tvin_cuva_data_s));
}
break;
#else
switch (rx.vs_info_details.vsi_state) {
case E_VSI_HDR10PLUS:
prop->hdr10p_info.hdr10p_on = rx.vs_info_details.hdr10plus;
@@ -1073,6 +1116,7 @@ void hdmirx_get_vsi_info(struct tvin_sig_property_s *prop)
sizeof(struct tvin_dv_vsif_raw_s) - 4);
}
break;
#endif
case E_VSI_4K3D:
if (hdmirx_hw_get_3d_structure() == 1) {
if (rx.vs_info_details._3d_structure == 0x1) {
@@ -1153,7 +1197,7 @@ void hdmirx_get_latency_info(struct tvin_sig_property_s *prop)
prop->latency.it_content = rx.cur.it_content;
prop->latency.cn_type = rx.cur.cn_type;
#ifdef CONFIG_AMLOGIC_HDMITX
if (rx.open_fg && rx.chip_id == CHIP_ID_T7 &&
if (rx.open_fg &&
(latency_info.allm_mode != rx.vs_info_details.hdmi_allm ||
latency_info.it_content != rx.cur.it_content ||
latency_info.cn_type != rx.cur.cn_type)) {
@@ -1166,7 +1210,7 @@ void hdmirx_get_latency_info(struct tvin_sig_property_s *prop)
}
static u32 emp_irq_cnt;
void hdmirx_get_emp_info(struct tvin_sig_property_s *prop)
void hdmirx_get_emp_dv_info(struct tvin_sig_property_s *prop)
{
//emp buffer not only stores DV_EMP packet, but also other packets.
//only DV_EMP is needed here
@@ -1174,9 +1218,9 @@ void hdmirx_get_emp_info(struct tvin_sig_property_s *prop)
return;
prop->emp_data.size = rx.vs_info_details.emp_pkt_cnt;
if (rx.vs_info_details.emp_pkt_cnt)
if (rx.emp_dv_info.dv_size)
memcpy(&prop->emp_data.empbuf,
emp_buf, rx.vs_info_details.emp_pkt_cnt * 32);
rx.emp_dv_info.dv_addr, rx.emp_dv_info.dv_size * 32);
#ifndef HDMIRX_SEND_INFO_TO_VDIN
if (emp_irq_cnt == rx.emp_buff.irq_cnt)
rx.vs_info_details.emp_pkt_cnt = 0;
@@ -1192,6 +1236,24 @@ void hdmirx_get_vtem_info(struct tvin_sig_property_s *prop)
&rx.vtem_info, sizeof(struct vtem_info_s));
}
void hdmirx_get_sbtm_info(struct tvin_sig_property_s *prop)
{
memset(&prop->sbtm_data, 0, sizeof(struct tvin_sbtm_data_s));
if (rx.sbtm_info.flag)
memcpy(&prop->sbtm_data,
&rx.sbtm_info, sizeof(struct sbtm_info_s));
}
void hdmirx_get_cuva_emds_info(struct tvin_sig_property_s *prop)
{
if (rx.emp_cuva_info.cuva_emds_size > sizeof(prop->cuva_emds_data))
rx_pr("cuva emds size exceeds 96 bytes\n");
memset(&prop->cuva_emds_data, 0, sizeof(prop->cuva_emds_data));
if (rx.emp_cuva_info.flag)
memcpy(&prop->cuva_emds_data, rx.emp_cuva_info.emds_addr,
sizeof(prop->cuva_emds_data));
}
void rx_set_sig_info(void)
{
struct tvin_frontend_s *fe = tvin_get_frontend(TVIN_PORT_HDMI0,
@@ -1205,14 +1267,10 @@ void rx_set_sig_info(void)
void rx_update_sig_info(void)
{
//if ((rx_vdin_level & 0x1) == 1)
rx_get_vsi_info();
//if (((rx_vdin_level >> 1) & 0x1) == 1)
rx_get_vtem_info();
//if (((rx_vdin_level >> 2) & 0x1) == 1)
rx_get_aif_info();
//if (((rx_vdin_level >> 3) & 0x1) == 1)
rx_set_sig_info();
rx_get_vsi_info();
rx_get_em_info();
rx_get_aif_info();
rx_set_sig_info();
}
/*
@@ -1220,12 +1278,12 @@ void rx_update_sig_info(void)
*/
void hdmirx_get_hdr_info(struct tvin_sig_property_s *prop)
{
struct drm_infoframe_st *drmpkt;
struct drm_infoframe_st *drm_pkt;
/*check drm packet is attach every VS*/
u32 drm_attach = rx_pkt_chk_attach_drm();
drmpkt = (struct drm_infoframe_st *)&rx_pkt.drm_info;
drm_pkt = (struct drm_infoframe_st *)&rx_pkt.drm_info;
if (drm_attach) {
rx.hdr_info.hdr_state = HDR_STATE_SET;
@@ -1250,39 +1308,39 @@ void hdmirx_get_hdr_info(struct tvin_sig_property_s *prop)
if (rx_pkt_chk_busy_drm())
break;
prop->hdr_info.hdr_data.length = drmpkt->length;
prop->hdr_info.hdr_data.eotf = drmpkt->des_u.tp1.eotf;
prop->hdr_info.hdr_data.length = drm_pkt->length;
prop->hdr_info.hdr_data.eotf = drm_pkt->des_u.tp1.eotf;
prop->hdr_info.hdr_data.metadata_id =
drmpkt->des_u.tp1.meta_des_id;
drm_pkt->des_u.tp1.meta_des_id;
prop->hdr_info.hdr_data.primaries[0].x =
drmpkt->des_u.tp1.dis_pri_x0;
drm_pkt->des_u.tp1.dis_pri_x0;
prop->hdr_info.hdr_data.primaries[0].y =
drmpkt->des_u.tp1.dis_pri_y0;
drm_pkt->des_u.tp1.dis_pri_y0;
prop->hdr_info.hdr_data.primaries[1].x =
drmpkt->des_u.tp1.dis_pri_x1;
drm_pkt->des_u.tp1.dis_pri_x1;
prop->hdr_info.hdr_data.primaries[1].y =
drmpkt->des_u.tp1.dis_pri_y1;
drm_pkt->des_u.tp1.dis_pri_y1;
prop->hdr_info.hdr_data.primaries[2].x =
drmpkt->des_u.tp1.dis_pri_x2;
drm_pkt->des_u.tp1.dis_pri_x2;
prop->hdr_info.hdr_data.primaries[2].y =
drmpkt->des_u.tp1.dis_pri_y2;
drm_pkt->des_u.tp1.dis_pri_y2;
prop->hdr_info.hdr_data.white_points.x =
drmpkt->des_u.tp1.white_points_x;
drm_pkt->des_u.tp1.white_points_x;
prop->hdr_info.hdr_data.white_points.y =
drmpkt->des_u.tp1.white_points_y;
drm_pkt->des_u.tp1.white_points_y;
prop->hdr_info.hdr_data.master_lum.x =
drmpkt->des_u.tp1.max_dislum;
drm_pkt->des_u.tp1.max_dislum;
prop->hdr_info.hdr_data.master_lum.y =
drmpkt->des_u.tp1.min_dislum;
drm_pkt->des_u.tp1.min_dislum;
prop->hdr_info.hdr_data.mcll =
drmpkt->des_u.tp1.max_light_lvl;
drm_pkt->des_u.tp1.max_light_lvl;
prop->hdr_info.hdr_data.mfall =
drmpkt->des_u.tp1.max_fa_light_lvl;
drm_pkt->des_u.tp1.max_fa_light_lvl;
prop->hdr_info.hdr_data.rawdata[0] = 0x87;
prop->hdr_info.hdr_data.rawdata[1] = 0x1;
prop->hdr_info.hdr_data.rawdata[2] = drmpkt->length;
prop->hdr_info.hdr_data.rawdata[2] = drm_pkt->length;
memcpy(&prop->hdr_info.hdr_data.rawdata[3],
&drmpkt->des_u.payload, 28);
&drm_pkt->des_u.payload, 28);
/* vdin can read current hdr data */
prop->hdr_info.hdr_state = HDR_STATE_GET;
}
@@ -1313,8 +1371,10 @@ void hdmirx_get_sig_property(struct tvin_frontend_s *fe,
hdmirx_get_vsi_info(prop);
hdmirx_get_spd_info(prop);
hdmirx_get_latency_info(prop);
hdmirx_get_emp_info(prop);
hdmirx_get_emp_dv_info(prop);
hdmirx_get_vtem_info(prop);
hdmirx_get_sbtm_info(prop);
hdmirx_get_cuva_emds_info(prop);
hdmirx_get_active_aspect_ratio(prop);
hdmirx_get_hdcp_sts(prop);
hdmirx_get_hw_vic(prop);
@@ -1395,7 +1455,7 @@ static long hdmirx_ioctl(struct file *file, unsigned int cmd,
struct pd_infoframe_s pkt_info;
struct spd_infoframe_st *spd_pkt;
unsigned int pin_status;
void *srcbuff;
void *src_buff;
u8 sad_data[30];
u8 len = 0;
u8 i = 0;
@@ -1404,7 +1464,7 @@ static long hdmirx_ioctl(struct file *file, unsigned int cmd,
pr_err("%s invalid command: %u\n", __func__, cmd);
return -EINVAL;
}
srcbuff = &pkt_info;
src_buff = &pkt_info;
devp = file->private_data;
switch (cmd) {
case HDMI_IOC_HDCP_GET_KSV:{
@@ -1515,13 +1575,13 @@ static long hdmirx_ioctl(struct file *file, unsigned int cmd,
//break;
// }
//memset(&pkt_info, 0, sizeof(pkt_info));
//srcbuff = &pkt_info;
//src_buff = &pkt_info;
//size = sizeof(struct pd_infoframe_s);
//rx_get_pd_fifo_param(param, &pkt_info);
/*return pkt info*/
//if (size > 0 && !argp) {
//if (copy_to_user(argp, srcbuff, size)) {
//if (copy_to_user(argp, src_buff, size)) {
//pr_err("get pd fifo param err\n");
//ret = -EFAULT;
//}
@@ -2368,7 +2428,6 @@ static DEVICE_ATTR_RW(reset22);
static DEVICE_ATTR_RW(hdcp_version);
static DEVICE_ATTR_RW(hw_info);
//static DEVICE_ATTR_RW(edid_dw);
//static DEVICE_ATTR_RW(ksvlist);
static DEVICE_ATTR_RW(earc_cap_ds);
static DEVICE_ATTR_RW(edid_select);
static DEVICE_ATTR_RW(audio_blk);
@@ -2405,7 +2464,7 @@ static struct device *hdmirx_create_device(struct device *parent, int id)
TVHDMI_DEVICE_NAME);
/* @to do this after Middleware API modified */
/*return device_create(hdmirx_clsp, parent, devno, NULL, "%s",*/
/*TVHDMI_DEVICE_NAME); */
/*TV_HDMI_DEVICE_NAME); */
}
static void hdmirx_delete_device(int minor)
@@ -2543,7 +2602,7 @@ void rx_emp_resource_allocate(struct device *dev)
//page_address
rx_pr("buff_a paddr=0x%p\n",
(void *)rx.emp_buff.p_addr_a);
rx_pr("buffb paddr=0x%p\n",
rx_pr("buff_b paddr=0x%p\n",
(void *)rx.emp_buff.p_addr_b);
} else {
rx_pr("emp buff err-1\n");
@@ -2759,7 +2818,7 @@ static int rx_vrr_notify_handler(struct notifier_block *nb,
memcpy(&vdata, p, sizeof(struct vrr_notifier_data_s));
rx.vrr_min = vdata.dev_vfreq_min;
rx.vrr_max = vdata.dev_vfreq_max;
rx_pr("%s: vrrmin=%d, vrrmax=%d\n", __func__, rx.vrr_min, rx.vrr_max);
rx_pr("%s: vrr_min=%d, vrr_max=%d\n", __func__, rx.vrr_min, rx.vrr_max);
break;
default:
ret = -EINVAL;
@@ -2819,7 +2878,7 @@ static int hdmirx_probe(struct platform_device *pdev)
/*get compatible matched device, to get chip related data*/
of_id = of_match_device(hdmirx_dt_match, &pdev->dev);
if (!of_id) {
rx_pr("t5m unable to get matched device\n");
rx_pr("unable to get matched device\n");
return -1;
}
/* allocate memory for the per-device structure */
@@ -2831,14 +2890,14 @@ static int hdmirx_probe(struct platform_device *pdev)
}
memset(hdevp, 0, sizeof(struct hdmirx_dev_s));
hdevp->data = of_id->data;
rx.hdmirxdev = hdevp;
rx.hdmirx_dev = hdevp;
if (hdevp->data) {
rx.chip_id = hdevp->data->chip_id;
rx.phy_ver = hdevp->data->phy_ver;
rx.port_num = hdevp->data->port_num;
rx_pr("chip id:%d\n", rx.chip_id);
rx_pr("phy ver:%d\n", rx.hdmirxdev->data->phy_ver);
rx_pr("phy ver:%d\n", rx.hdmirx_dev->data->phy_ver);
} else {
/*txlx chip for default*/
rx.chip_id = CHIP_ID_TXLX;
@@ -2943,11 +3002,6 @@ static int hdmirx_probe(struct platform_device *pdev)
//rx_pr("hdmirx: fail to create edid_dw file\n");
//goto fail_create_edid_dw;
//}
//ret = device_create_file(hdevp->dev, &dev_attr_ksvlist);
//if (ret < 0) {
// rx_pr("hdmirx: fail to create ksvlist file\n");
// goto fail_create_ksvlist;
//}
ret = device_create_file(hdevp->dev, &dev_attr_earc_cap_ds);
if (ret < 0) {
rx_pr("hdmirx: fail to create earc_cap_ds file\n");
@@ -2984,10 +3038,6 @@ static int hdmirx_probe(struct platform_device *pdev)
goto fail_create_hdcp22_onoff;
}
ret = device_create_file(hdevp->dev, &dev_attr_mode);
if (ret < 0) {
rx_pr("hdmirx: fail to create hdcp_auth_sts file\n");
goto fail_create_hdcp_auth_sts;
}
if (ret < 0) {
rx_pr("hdmirx: fail to create mode file\n");
goto fail_create_mode;
@@ -3012,6 +3062,11 @@ static int hdmirx_probe(struct platform_device *pdev)
rx_pr("hdmirx: fail to create hdmi_hdr_status file\n");
goto fail_create_hdmi_hdr_status;
}
ret = device_create_file(hdevp->dev, &dev_attr_hdcp_auth_sts);
if (ret < 0) {
rx_pr("hdmirx: fail to create hdcp_auth_sts file\n");
goto fail_create_hdcp_auth_sts;
}
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res) {
rx_pr("%s: can't get irq resource\n", __func__);
@@ -3021,7 +3076,7 @@ static int hdmirx_probe(struct platform_device *pdev)
hdevp->irq = res->start;
snprintf(hdevp->irq_name, sizeof(hdevp->irq_name),
"hdmirx%d-irq", hdevp->index);
rx_pr("hdevpd irq: %d, %d\n", hdevp->index,
rx_pr("hdevp irq: %d, %d\n", hdevp->index,
hdevp->irq);
if (request_irq(hdevp->irq,
&irq_handler,
@@ -3211,8 +3266,8 @@ static int hdmirx_probe(struct platform_device *pdev)
/* queue_delayed_work(eq_wq, &eq_dwork, msecs_to_jiffies(5)); */
}
/* create for aml phy init */
amlphy_wq = create_workqueue(hdevp->frontend.name);
INIT_WORK(&amlphy_dwork, aml_phy_init_handler);
aml_phy_wq = create_workqueue(hdevp->frontend.name);
INIT_WORK(&aml_phy_dwork, aml_phy_init_handler);
/* create for clk msr */
clkmsr_wq = create_workqueue(hdevp->frontend.name);
@@ -3231,7 +3286,6 @@ static int hdmirx_probe(struct platform_device *pdev)
rx_pr("en_4k_2_2k not found.\n");
en_4k_2_2k = 0;
}
ret = of_property_read_u32(pdev->dev.of_node,
"en_4k_timing", &en_4k_timing);
if (ret)
@@ -3289,8 +3343,8 @@ static int hdmirx_probe(struct platform_device *pdev)
rx_pr("not find rpt_only_mode, soundbar by default\n");
}
ret = of_property_read_u32(pdev->dev.of_node,
"disable_hdr",
&disable_hdr);
"disable_hdr",
&disable_hdr);
if (ret) {
disable_hdr = 0;
rx_pr("not find disable_hdr, hdr enable by default\n");
@@ -3358,6 +3412,7 @@ fail_kmalloc_pd_fifo:
return ret;
fail_get_resource_irq:
return ret;
fail_create_hdcp_auth_sts:
device_remove_file(hdevp->dev, &dev_attr_hdcp_auth_sts);
fail_create_hdmi_hdr_status:
@@ -3384,10 +3439,8 @@ fail_create_vrr_func_ctrl:
device_remove_file(hdevp->dev, &dev_attr_vrr_func_ctrl);
fail_create_earc_cap_ds:
device_remove_file(hdevp->dev, &dev_attr_earc_cap_ds);
//fail_create_ksvlist:
//device_remove_file(hdevp->dev, &dev_attr_ksvlist);
//fail_create_edid_dw:
//device_remove_file(hdevp->dev, &dev_attr_edid_dw);
// device_remove_file(hdevp->dev, &dev_attr_edid_dw);
fail_create_hw_info:
device_remove_file(hdevp->dev, &dev_attr_hw_info);
fail_create_hdcp_version:
@@ -3440,8 +3493,8 @@ static int hdmirx_remove(struct platform_device *pdev)
cancel_delayed_work_sync(&esm_dwork);
destroy_workqueue(esm_wq);
cancel_work_sync(&amlphy_dwork);
destroy_workqueue(amlphy_wq);
cancel_work_sync(&aml_phy_dwork);
destroy_workqueue(aml_phy_wq);
#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
unregister_early_suspend(&hdmirx_early_suspend_handler);
#endif
@@ -3468,7 +3521,6 @@ static int hdmirx_remove(struct platform_device *pdev)
device_remove_file(hdevp->dev, &dev_attr_info);
device_remove_file(hdevp->dev, &dev_attr_arc_aud_type);
device_remove_file(hdevp->dev, &dev_attr_earc_cap_ds);
//device_remove_file(hdevp->dev, &dev_attr_ksvlist);
//device_remove_file(hdevp->dev, &dev_attr_edid_dw);
device_remove_file(hdevp->dev, &dev_attr_hw_info);
device_remove_file(hdevp->dev, &dev_attr_hdcp_version);
drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+61 -20
View File
@@ -48,6 +48,14 @@
/* fix conflict between two delay work */
#define RX_VER1 "ver.2023/3/2"
/*
* Currently, a total of 5 VSIF packages are supported,
* DV/HDR10+/CUVA/HDMI2.1/HDMI1.4, but only the last one can be parsed
* each time. The purpose of MULTI_VSIF_EXPORT_TO_EMP is to transfer the
* optimal VSIF packet to VDIN when multiple VSIF packets are received.
*/
#define MULTI_VSIF_EXPORT_TO_EMP
/* 50ms timer for hdmirx main loop (HDMI_STATE_CHECK_FREQ is 20) */
#define TIME_1MS 1000000
@@ -62,6 +70,9 @@
#define PFIFO_SIZE 160
#define HDCP14_KEY_SIZE 368
/* sizeof(emp_buf) / sizeof(sizeof(struct pd_infoframe_s) + 1) = 1024/32 */
#define EMP_DSF_CNT_MAX 32
//#define SPECIAL_FUNC_EN
#ifdef SPECIAL_FUNC_EN
//bit0 portA bit1 portB bit2 portC
@@ -477,7 +488,7 @@ struct hdmi_rx_hdcp {
* @note 0: high order, 1: low order
*/
u32 keys[HDCP_KEYS_SIZE];
struct extcon_dev *rx_excton_auth;
struct extcon_dev *rx_extcon_auth;
enum hdcp_version_e hdcp_version;/* 0 no hdcp;1 hdcp14;2 hdcp22 */
/* add for dv cts */
enum hdcp_version_e hdcp_pre_ver;
@@ -503,13 +514,17 @@ struct vsi_info_s {
bool dv_allm;
bool hdmi_allm;
bool hdr10plus;
bool cuva_hdr;
u8 ccbpc;
u8 vsi_state;
u8 vsi_state; // bit0-5: 4K3D/VSI21/HDR10+/DV10/DV15/CUVA
u8 emp_pkt_cnt;
u8 timeout;
u8 max_frl_rate;
u8 sys_start_code;
u8 cuva_version_code;
};
//===============emp start
struct vtem_info_s {
u8 vrr_en;
u8 m_const;
@@ -518,19 +533,37 @@ struct vtem_info_s {
u8 base_vfront;
u8 rb;
u16 base_framerate;
//real structure
//u8 vrr_en:1;
//u8 m_const:1;
//u8 qms_en;
//u8 rsvd0:1;
//u8 fva_factor_m1:4;
//u8 base_vfront;
//u8 base_fr_high:2;
//u8 rb:1;
//u8 rsvd1:5;
//u8 base_fr_low;
};
struct sbtm_info_s {
u8 flag;
u8 sbtm_ver;
u8 sbtm_mode;
u8 sbtm_type;
u8 grdm_min;
u8 grdm_lum;
u16 frm_pb_limit_int;
};
struct cuva_emds_s {
bool flag;
unsigned char *emds_addr;
u8 cuva_emds_size;
};
struct dv_info_s {
bool flag;
unsigned char *dv_addr;
u8 dv_size;
};
struct emp_dsf_st {
int pkt_cnt;
u8 *pkt_addr;
};
//================emp end
#define CHANNEL_STATUS_SIZE 24
struct aud_info_s {
@@ -608,6 +641,7 @@ struct emp_buff {
void __iomem *ready;
unsigned long irq_cnt;
unsigned int emp_pkt_cnt;
unsigned int pre_emp_pkt_cnt;
unsigned int tmds_pkt_cnt;
bool end;
u8 ogi_id;
@@ -641,7 +675,7 @@ int hdmirx_set_uevent(enum hdmirx_event type, int val);
struct rx_s {
enum chip_id_e chip_id;
enum phy_ver_e phy_ver;
struct hdmirx_dev_s *hdmirxdev;
struct hdmirx_dev_s *hdmirx_dev;
/** HDMI RX received signal changed */
u32 skip;
/*avmute*/
@@ -660,12 +694,11 @@ struct rx_s {
bool open_fg;
bool cableclk_stb_flg;
u8 irq_flag;
bool firm_change;/*hdcp2.2 rp/rx switch time*/
/** HDMI RX controller HDCP configuration */
struct hdmi_rx_hdcp hdcp;
/*report hpd status to app*/
struct extcon_dev *rx_excton_rx22;
struct extcon_dev *rx_excton_open;
struct extcon_dev *rx_extcon_rx22;
struct extcon_dev *rx_extcon_open;
/* wrapper */
unsigned int state;
@@ -692,6 +725,13 @@ struct rx_s {
struct vsi_info_s vs_info_details;
struct tvin_hdr_info_s hdr_info;
struct vtem_info_s vtem_info;
struct sbtm_info_s sbtm_info;
struct cuva_emds_s emp_cuva_info;
struct dv_info_s emp_dv_info;
u8 emp_dsf_cnt;
bool emp_pkt_rev;
bool new_emp_pkt;
struct emp_dsf_st emp_dsf_info[EMP_DSF_CNT_MAX];
unsigned char edid_mix_buf[EDID_MIX_MAX_SIZE];
unsigned int pwr_sts;
/* for debug */
@@ -709,6 +749,7 @@ struct rx_s {
u8 free_sync_sts;
u8 afifo_sts;
u32 ecc_err;
u32 ecc_pkt_cnt;
u32 ecc_err_frames_cnt;
bool ddc_filter_en;
unsigned char port_num;
@@ -743,8 +784,8 @@ extern struct workqueue_struct *eq_wq;
extern struct delayed_work esm_dwork;
extern struct workqueue_struct *esm_wq;
extern struct delayed_work repeater_dwork;
extern struct work_struct amlphy_dwork;
extern struct workqueue_struct *amlphy_wq;
extern struct work_struct aml_phy_dwork;
extern struct workqueue_struct *aml_phy_wq;
extern struct work_struct clkmsr_dwork;
extern struct workqueue_struct *clkmsr_wq;
extern struct work_struct earc_hpd_dwork;
@@ -784,7 +825,7 @@ extern int rgb_quant_range;
extern int yuv_quant_range;
extern int en_4k_timing;
extern int cec_dev_en;
extern bool dev_is_appletv_v2;
extern bool dev_is_apple_tv_v2;
extern u32 en_4096_2_3840;
extern int en_4k_2_2k;
extern bool hdmi_cec_en;
drivers/media/vin/tvin/hdmirx/hdmi_rx_edid.c
+8 -6
View File
@@ -1654,7 +1654,7 @@ void rx_edid_update_overlay(u_int *phy_addr_offset,
/* @func: seek dd+ atmos bit
* @param:get audio type info by cec message:
* request short sudio descriptor
* request short audio descriptor
*/
unsigned char rx_parse_arc_aud_type(const unsigned char *buff)
{
@@ -1957,8 +1957,10 @@ static void rx_edid_update_vsvdb(u_char *pedid,
/* if len = 0xFF, revert to original edid, no change */
if (!pedid || !add_data || len == 0xFF)
return;
if (hdmirx_repeat_support())
return;
/* if len = 0, means disable.
* now only consider VSVDB of DV, not HDR10+
*/
@@ -3207,7 +3209,7 @@ static void get_edid_dv_data(unsigned char *buff,
buff[start + 4] & 0x1;
edid_info->dv_vsvdb.target_min_lum =
(buff[start + 5] >> 1) & 0x7F;
edid_info->dv_vsvdb.colormetry =
edid_info->dv_vsvdb.colorimetry =
buff[start + 5] & 0x1;
edid_info->dv_vsvdb.Rx = buff[start + 7];
edid_info->dv_vsvdb.Ry = buff[start + 8];
@@ -3996,8 +3998,8 @@ void rx_parse_print_vsvdb(struct dv_vsvdb_s *dv_vsvdb)
dv_vsvdb->target_max_lum);
rx_pr("target_min_lum: 0x%x\n",
dv_vsvdb->target_min_lum);
rx_pr("colormetry: 0x%x\n",
dv_vsvdb->colormetry);
rx_pr("colorimetry: 0x%x\n",
dv_vsvdb->colorimetry);
}
}
@@ -4428,7 +4430,7 @@ void earc_cap_ds_index_print(struct earc_cap_ds *cap_info)
if (!cap_info)
return;
rx_pr("****eARC Cap Data Sturct Index****\n");
rx_pr("****eARC Cap Data Struct Index****\n");
rx_pr("cap_ds_len: %d\n", cap_info->cap_ds_len);
rx_pr("cap_ds_ver: %d\n", cap_info->cap_ds_ver);
if (cap_info->cap_ds_len > 1)
@@ -4788,7 +4790,7 @@ void splice_tag_db_to_edid(u8 *p_edid, u8 *add_buf,
splice_data_blk_to_edid(p_edid, tag_data_blk, 0xFF);
}
/* romove cta data blk which tag = tagid */
/* remove cta data blk which tag = tagid */
void edid_rm_db_by_tag(u8 *p_edid, u16 tagid)
{
int tag_offset;
drivers/media/vin/tvin/hdmirx/hdmi_rx_edid.h
+9 -8
View File
@@ -124,7 +124,7 @@ union bit_rate_u {
unsigned char size_16bit:1;
unsigned char size_20bit:1;
unsigned char size_24bit:1;
unsigned char size_reserv:5;
unsigned char size_reserved:5;
} pcm;
unsigned char others;
};
@@ -132,7 +132,7 @@ union bit_rate_u {
struct edid_audio_block_t {
unsigned char max_channel:3;
unsigned char format_code:4;
unsigned char fmt_code_resvrd:1;
unsigned char fmt_code_reserved:1;
union u_sr {
unsigned char freq_list;
struct s_sr {
@@ -143,7 +143,7 @@ struct edid_audio_block_t {
unsigned char freq_96khz:1;
unsigned char freq_176_4khz:1;
unsigned char freq_192khz:1;
unsigned char freq_reserv:1;
unsigned char freq_reserved:1;
} ssr;
} usr;
union bit_rate_u bit_rate;
@@ -156,7 +156,7 @@ struct edid_hdr_block_t {
unsigned char smtpe_2048:1;
unsigned char future:5;
unsigned char meta_des_type1:1;
unsigned char reserv:7;
unsigned char reserved:7;
unsigned char max_lumi;
unsigned char avg_lumi;
unsigned char min_lumi;
@@ -230,7 +230,7 @@ struct specific_vic_3d {
unsigned char _2d_vic_order:4;
unsigned char _3d_struct:4;
unsigned char _3d_detail:4;
unsigned char resrvd:4;
unsigned char reserved:4;
};
struct vsdb_s {
@@ -283,7 +283,7 @@ struct vsdb_s {
unsigned char interlaced_video_latency;
unsigned char interlaced_audio_latency;
//pb10
unsigned char rsv3:3;
unsigned char resrvd3:3;
unsigned char image_size:2;
unsigned char _3d_multi_present:2;
unsigned char _3d_present:1;
@@ -442,9 +442,9 @@ struct dv_vsvdb_s {
unsigned char sup_global_dimming:1;
unsigned char target_min_lum:7;
unsigned char colormetry:1;
unsigned char colorimetry:1;
unsigned char resrvd;
unsigned char reserved;
u16 Rx;
u16 Ry;
u16 Gx;
@@ -852,6 +852,7 @@ u_int rx_get_cea_tag_offset(u8 *cur_edid, u16 tag_code);
void get_edid_standard_timing_info(u8 *p_edid, struct edid_standard_timing *edid_st_info);
void rm_unsupported_st(u8 *p_edid,
struct edid_standard_timing *edid_st_info, unsigned int refresh_rate);
#ifdef CONFIG_AMLOGIC_HDMITX
bool rx_update_tx_edid_with_audio_block(unsigned char *edid_data,
unsigned char *audio_block);
drivers/media/vin/tvin/hdmirx/hdmi_rx_eq.c
+53 -53
View File
@@ -53,7 +53,7 @@ int eq_dbg_ch2;
u32 phy_pddq_en;
/*------------------------variable define end----------------------*/
bool eq_maxvsmin(int ch0setting, int ch1setting, int ch2setting)
bool eq_max_vs_min(int ch0setting, int ch1setting, int ch2setting)
{
int min = ch0setting;
int max = ch0setting;
@@ -73,19 +73,19 @@ bool eq_maxvsmin(int ch0setting, int ch1setting, int ch2setting)
return 1;
}
void initvars(struct st_eq_data *ch_data)
void init_vars(struct st_eq_data *ch_data)
{
/* Slope accumulator */
ch_data->acc = 0;
/* Early Counter dataAcquisition data */
ch_data->acq = 0;
ch_data->lastacq = 0;
ch_data->validlongsetting = 0;
ch_data->validshortsetting = 0;
ch_data->last_acq = 0;
ch_data->valid_long_setting = 0;
ch_data->valid_short_setting = 0;
/* BEST Setting = short */
ch_data->bestsetting = SHORTCABLESETTING;
/* TMDS VALID not valid */
ch_data->tmdsvalid = 0;
ch_data->tmds_valid = 0;
memset(ch_data->acq_n, 0, sizeof(u16) * 15);
}
@@ -112,17 +112,17 @@ void hdmi_rx_phy_confequalautocalib(void)
hdmirx_wr_phy(PHY_MAINFSM_CTL, 0x1809);
}
u16 rx_phy_rd_earlycnt_ch0(void)
u16 rx_phy_rd_early_cnt_ch0(void)
{
return hdmirx_rd_phy(PHY_EQSTAT3_CH0);
}
u16 rx_phy_rd_earlycnt_ch1(void)
u16 rx_phy_rd_early_cnt_ch1(void)
{
return hdmirx_rd_phy(PHY_EQSTAT3_CH1);
}
u16 rx_phy_rd_earlycnt_ch2(void)
u16 rx_phy_rd_early_cnt_ch2(void)
{
return hdmirx_rd_phy(PHY_EQSTAT3_CH2);
}
@@ -172,7 +172,7 @@ void eq_dwork_handler(struct work_struct *work)
eq_ch1.bestsetting,
eq_ch2.bestsetting);
if (eq_maxvsmin(eq_ch0.bestsetting,
if (eq_max_vs_min(eq_ch0.bestsetting,
eq_ch1.bestsetting,
eq_ch2.bestsetting) == 1) {
eq_sts = E_EQ_PASS;
@@ -235,39 +235,39 @@ u8 testtype(u16 setting, struct st_eq_data *ch_data)
{
u16 stepslope = 0;
/* LONG CABLE EQUALIZATION */
if (ch_data->acq < ch_data->lastacq &&
ch_data->tmdsvalid == 1) {
ch_data->acc += (ch_data->lastacq - ch_data->acq);
if (ch_data->validlongsetting == 0 &&
if (ch_data->acq < ch_data->last_acq &&
ch_data->tmds_valid == 1) {
ch_data->acc += (ch_data->last_acq - ch_data->acq);
if (ch_data->valid_long_setting == 0 &&
ch_data->acq < EQUALIZEDCOUNTERVALUE &&
ch_data->acc > ACCMINLIMIT) {
ch_data->bestlongsetting = setting;
ch_data->validlongsetting = 1;
ch_data->best_long_setting = setting;
ch_data->valid_long_setting = 1;
}
stepslope = ch_data->lastacq - ch_data->acq;
stepslope = ch_data->last_acq - ch_data->acq;
}
/* SHORT CABLE EQUALIZATION */
if (ch_data->tmdsvalid == 1 &&
ch_data->validshortsetting == 0) {
if (ch_data->tmds_valid == 1 &&
ch_data->valid_short_setting == 0) {
/* Short setting better than default, system over-equalized */
if (setting < SHORTCABLESETTING &&
ch_data->acq < EQUALIZEDCOUNTERVALUE) {
ch_data->validshortsetting = 1;
ch_data->bestshortsetting = setting;
ch_data->valid_short_setting = 1;
ch_data->best_short_setting = setting;
}
/* default Short setting is valid */
if (setting == SHORTCABLESETTING) {
ch_data->validshortsetting = 1;
ch_data->bestshortsetting = SHORTCABLESETTING;
ch_data->valid_short_setting = 1;
ch_data->best_short_setting = SHORTCABLESETTING;
}
}
/* Exit type Long cable
* (early-late count curve well behaved
* and 50% threshold achived)
*/
if (ch_data->validlongsetting == 1 &&
ch_data->acc > ACCLIMIT) {
ch_data->bestsetting = ch_data->bestlongsetting;
if (ch_data->valid_long_setting == 1 &&
ch_data->acc > ACC_LIMIT) {
ch_data->bestsetting = ch_data->best_long_setting;
if (ch_data->bestsetting > long_cable_best_setting)
ch_data->bestsetting = long_cable_best_setting;
if (log_level & EQ_LOG)
@@ -278,9 +278,9 @@ u8 testtype(u16 setting, struct st_eq_data *ch_data)
* (early-late count curve behaved as a short cable)
*/
if (setting == eq_max_setting &&
ch_data->acc < ACCLIMIT &&
ch_data->validshortsetting == 1) {
ch_data->bestsetting = ch_data->bestshortsetting;
ch_data->acc < ACC_LIMIT &&
ch_data->valid_short_setting == 1) {
ch_data->bestsetting = ch_data->best_short_setting;
if (log_level & EQ_LOG)
rx_pr("shortcable");
return E_SHORT_CABLE;
@@ -290,8 +290,8 @@ u8 testtype(u16 setting, struct st_eq_data *ch_data)
* nevertheless 50% threshold not achieved
*/
if (setting == eq_max_setting &&
ch_data->tmdsvalid == 1 &&
ch_data->acc > ACCLIMIT &&
ch_data->tmds_valid == 1 &&
ch_data->acc > ACC_LIMIT &&
stepslope > MINSLOPE) {
ch_data->bestsetting = long_cable_best_setting;
if (log_level & EQ_LOG)
@@ -311,7 +311,7 @@ u8 testtype(u16 setting, struct st_eq_data *ch_data)
return E_CABLE_NOT_FOUND;
}
u8 aquireearlycnt(u16 setting)
u8 aquire_early_cnt(u16 setting)
{
u16 stepslope = 0x0001;
int timeout_cnt = 10;
@@ -322,22 +322,22 @@ u8 aquireearlycnt(u16 setting)
/* mdelay(delay_ms_cnt); */
while (timeout_cnt--) {
mdelay(delay_ms_cnt);
eq_ch0.tmdsvalid =
eq_ch0.tmds_valid =
(hdmi_rx_phy_corestatusch0() & 0x0080) > 0 ? 1 : 0;
eq_ch1.tmdsvalid =
eq_ch1.tmds_valid =
(hdmi_rx_phy_corestatusch1() & 0x0080) > 0 ? 1 : 0;
eq_ch2.tmdsvalid =
eq_ch2.tmds_valid =
(hdmi_rx_phy_corestatusch2() & 0x0080) > 0 ? 1 : 0;
if ((eq_ch0.tmdsvalid |
eq_ch1.tmdsvalid |
eq_ch2.tmdsvalid) != 0)
if ((eq_ch0.tmds_valid |
eq_ch1.tmds_valid |
eq_ch2.tmds_valid) != 0)
break;
}
if ((eq_ch0.tmdsvalid |
eq_ch1.tmdsvalid |
eq_ch2.tmdsvalid) == 0) {
if ((eq_ch0.tmds_valid |
eq_ch1.tmds_valid |
eq_ch2.tmds_valid) == 0) {
if (log_level & EQ_LOG)
rx_pr("invalid-earlycnt\n");
rx_pr("invalid-early_cnt\n");
return 0;
}
@@ -350,15 +350,15 @@ u8 aquireearlycnt(u16 setting)
/* by per channel basis or global pin */
/* TMDS VALID BY channel basis (Option #1) */
/* Get early counters */
eq_ch0.acq = rx_phy_rd_earlycnt_ch0() >> AVGACQ;
eq_ch0.acq = rx_phy_rd_early_cnt_ch0() >> AVGACQ;
eq_ch0.acq_n[setting] = eq_ch0.acq;
if (log_level & ERR_LOG)
rx_pr("eq_ch0_acq #%d = %d\n", setting, eq_ch0.acq);
eq_ch1.acq = rx_phy_rd_earlycnt_ch1() >> AVGACQ;
eq_ch1.acq = rx_phy_rd_early_cnt_ch1() >> AVGACQ;
eq_ch1.acq_n[setting] = eq_ch1.acq;
if (log_level & ERR_LOG)
rx_pr("eq_ch1_acq #%d = %d\n", setting, eq_ch1.acq);
eq_ch2.acq = rx_phy_rd_earlycnt_ch2() >> AVGACQ;
eq_ch2.acq = rx_phy_rd_early_cnt_ch2() >> AVGACQ;
eq_ch2.acq_n[setting] = eq_ch2.acq;
if (log_level & ERR_LOG)
rx_pr("eq_ch2_acq #%d = %d\n", setting, eq_ch2.acq);
@@ -374,23 +374,23 @@ u8 settingfinder(void)
u16 retcodech2 = 0;
u8 tmds_valid = 0;
initvars(&eq_ch0);
initvars(&eq_ch1);
initvars(&eq_ch2);
init_vars(&eq_ch0);
init_vars(&eq_ch1);
init_vars(&eq_ch2);
/* Get statistics of early-late counters for setting 0 */
tmds_valid = aquireearlycnt(actsetting);
tmds_valid = aquire_early_cnt(actsetting);
while (retcodech0 == 0 || retcodech1 == 0 || retcodech2 == 0) {
actsetting++;
/* Update last acquisition value, */
/* for threshold crossing detection */
eq_ch0.lastacq = eq_ch0.acq;
eq_ch1.lastacq = eq_ch1.acq;
eq_ch2.lastacq = eq_ch2.acq;
eq_ch0.last_acq = eq_ch0.acq;
eq_ch1.last_acq = eq_ch1.acq;
eq_ch2.last_acq = eq_ch2.acq;
/* Get statistics of early-late */
/* counters for next setting */
tmds_valid = aquireearlycnt(actsetting);
tmds_valid = aquire_early_cnt(actsetting);
/* check for cable type, stop after detection */
if (retcodech0 == 0) {
retcodech0 = testtype(actsetting, &eq_ch0);
drivers/media/vin/tvin/hdmirx/hdmi_rx_eq.h
+10 -10
View File
@@ -6,11 +6,11 @@
#ifndef _HDMI_RX_EQ_H
#define _HDMI_RX_EQ_H
/* time mS */
#define WAITTIMESTARTCONDITIONS 3
/* WAIT FOR, CDR LOCK and TMDSVALID */
#define WAIT_TIMESTART_CONDITIONS 3
/* WAIT FOR, CDR LOCK and TMDS_VALID */
#define SLEEP_TIME_CDR 10
/* Maximum slope accumulator to consider the cable as a short cable */
#define ACCLIMIT 360
#define ACC_LIMIT 360
/* Minimum slope accumulator to consider the following setting */
#define ACCMINLIMIT 0
/* suitable for a long cable */
@@ -107,15 +107,15 @@ enum eq_cable_type_e {
struct st_eq_data {
/* Best long cable setting */
u16 bestlongsetting;
u16 best_long_setting;
/* long cable setting detected and valid */
u8 validlongsetting;
u8 valid_long_setting;
/* best short cable setting */
u16 bestshortsetting;
u16 best_short_setting;
/* best short cable setting detected and valid */
u8 validshortsetting;
u8 valid_short_setting;
/* TMDS Valid for channel */
u8 tmdsvalid;
u8 tmds_valid;
/* best setting to be programed */
u16 bestsetting;
/* Accumulator register */
@@ -123,7 +123,7 @@ struct st_eq_data {
/* Acquisition register */
u16 acq;
u16 acq_n[15];
u16 lastacq;
u16 last_acq;
u8 eq_ref[3];
};
@@ -143,7 +143,7 @@ extern enum eq_sts_e eq_sts;
int rx_eq_algorithm(void);
int hdmirx_phy_start_eq(void);
u8 settingfinder(void);
bool eq_maxvsmin(int ch0setting, int ch1setting, int ch2setting);
bool eq_max_vs_min(int ch0setting, int ch1setting, int ch2setting);
/* int hdmirx_phy_suspend_eq(void); */
bool hdmirx_phy_check_tmds_valid(void);
void hdmirx_phy_conf_eq_setting(int rx_port_sel,
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+164 -97
View File
@@ -50,7 +50,7 @@
#define HYST_HDMI_TO_DVI 5
/* must = 0, other agilent source fail */
#define HYST_DVI_TO_HDMI 0
#define GCP_GLOBAVMUTE_EN 1 /* ag506 must clear this bit */
#define GCP_GLOB_AVMUTE_EN 1 /* ag506 must clear this bit */
#define EDID_CLK_DIV 9 /* sys clk/(9+1) = 20M */
#define HDCP_KEY_WR_TRIES (5)
@@ -76,7 +76,7 @@ int aud_avmute_en = 1;
int aud_mute_sel = 2;
int force_clk_rate;
u32 rx_ecc_err_thres = 100;
u32 rx_ecc_err_frames = 50;
u32 rx_ecc_err_frames = 5;
int md_ists_en = VIDEO_MODE;
int pdec_ists_en;/* = AVI_CKS_CHG | DVIDET | DRM_CKS_CHG | DRM_RCV_EN;*/
u32 packet_fifo_cfg;
@@ -128,6 +128,7 @@ int kill_esm_fail;
/* emp buffer */
char emp_buf[1024];
char pre_emp_buf[1024];
int i2c_err_cnt;
u32 ddc_dbg_en;
/*------------------------variable define end------------------------------*/
@@ -1294,9 +1295,9 @@ void hdmirx_top_irq_en(int en, int lvl)
}
/*
* rx_get_audinfo - get aduio info
* rx_get_aud_info - get aduio info
*/
void rx_get_audinfo(struct aud_info_s *audio_info)
void rx_get_aud_info(struct aud_info_s *audio_info)
{
/* refer to hdmi spec. CT = 0 */
audio_info->coding_type = 0;
@@ -1482,7 +1483,7 @@ bool is_clk_stable(void)
rx.clk.cable_clk >= MIN_TMDS_CLK)
clk = rx.clk.cable_clk;
} else if (rx.chip_id >= CHIP_ID_TL1) {
/* sqofclk */
/* sqof_clk */
clk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
} else {
/* phy clk */
@@ -1508,7 +1509,7 @@ void rx_afifo_store_all_subpkt(bool all_pkt)
if (all_pkt) {
if (log_level & AUDIO_LOG)
rx_pr("afifo store all subpkts: %d\n", flag);
rx_pr("afifo store all sub_pkts: %d\n", flag);
/* when afifo overflow, try afifo store
* configuration alternatively
*/
@@ -1550,13 +1551,13 @@ unsigned int hdmirx_audio_fifo_rst(void)
int hdmirx_control_clk_range(unsigned long min, unsigned long max)
{
int error = 0;
unsigned int evaltime = 0;
unsigned int eval_time = 0;
unsigned long ref_clk;
ref_clk = modet_clk;
evaltime = (ref_clk * 4095) / 158000;
min = (min * evaltime) / ref_clk;
max = (max * evaltime) / ref_clk;
eval_time = (ref_clk * 4095) / 158000;
min = (min * eval_time) / ref_clk;
max = (max * eval_time) / ref_clk;
hdmirx_wr_bits_dwc(DWC_HDMI_CKM_F, MINFREQ, min);
hdmirx_wr_bits_dwc(DWC_HDMI_CKM_F, CKM_MAXFREQ, max);
return error;
@@ -1621,8 +1622,8 @@ int packet_init_t5(void)
data32 |= 1 << 4; /* PD_FIFO_WE */
data32 |= 0 << 1; /* emp pkt rev int,0:last 1:every */
data32 |= 1 << 0; /* PDEC_BCH_EN */
data32 &= (~GCP_GLOBAVMUTE);
data32 |= GCP_GLOBAVMUTE_EN << 15;
data32 &= (~GCP_GLOB_AVMUTE);
data32 |= GCP_GLOB_AVMUTE_EN << 15;
data32 |= packet_fifo_cfg;
hdmirx_wr_dwc(DWC_PDEC_CTRL, data32);
@@ -1639,6 +1640,7 @@ int packet_init_t7(void)
{
u8 data8 = 0;
#ifndef MULTI_VSIF_EXPORT_TO_EMP
/* vsif id check en */
hdmirx_wr_cor(VSI_CTRL2_DP3_IVCRX, 1);
/* vsif pkt id cfg, default is 000c03 */
@@ -1668,6 +1670,7 @@ int packet_init_t7(void)
/* use unrec to store hf-vsif */
hdmirx_wr_cor(RX_UNREC_CTRL_DP2_IVCRX, 1);
hdmirx_wr_cor(RX_UNREC_DEC_DP2_IVCRX, PKT_TYPE_INFOFRAME_VSI);
#endif
/* get data 0x11c0-11de */
data8 = 0;
@@ -1826,7 +1829,7 @@ static int TOP_init(void)
if (rx.chip_id >= CHIP_ID_T7) {
rx_hdcp22_wr_top(TOP_SECURE_MODE, 1);
/* Filter 100ns glitch */
hdmirx_wr_top(TOP_AUDPLL_LOCK_FILTER, 32);
hdmirx_wr_top(TOP_AUD_PLL_LOCK_FILTER, 32);
data32 = 0;
data32 |= (1 << 1);// [1:0] sel
hdmirx_wr_top(TOP_PHYIF_CNTL0, data32);
@@ -1883,7 +1886,7 @@ static int TOP_init(void)
data32 |= (0 << 24); /* [25:24] source_0 */
hdmirx_wr_top(TOP_CHAN_SWITCH_0, data32);
/* Configure TMDS algin T7 unused */
/* Configure TMDS align T7 unused */
data32 = 0;
hdmirx_wr_top(TOP_TMDS_ALIGN_CNTL0, data32);
data32 = 0;
@@ -1955,9 +1958,9 @@ static int DWC_init(void)
{
int err = 0;
unsigned long data32;
unsigned int evaltime = 0;
unsigned int eval_time = 0;
evaltime = (modet_clk * 4095) / 158000;
eval_time = (modet_clk * 4095) / 158000;
/* enable all */
hdmirx_wr_dwc(DWC_HDMI_OVR_CTRL, ~0);
/* recover to default value.*/
@@ -1968,7 +1971,7 @@ static int DWC_init(void)
/*hdmirx_wr_bits_dwc(DWC_HDMI_SYNC_CTRL,*/
/* HS_POL_ADJ_MODE, HS_POL_ADJ_AUTO);*/
hdmirx_wr_bits_dwc(DWC_HDMI_CKM_EVLTM, EVAL_TIME, evaltime);
hdmirx_wr_bits_dwc(DWC_HDMI_CKM_EVLTM, EVAL_TIME, eval_time);
hdmirx_control_clk_range(TMDS_CLK_MIN, TMDS_CLK_MAX);
/* hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,*/
@@ -2130,6 +2133,7 @@ void rx_hdcp14_config(const struct hdmi_rx_hdcp *hdcp)
bool rx_clr_tmds_valid(void)
{
bool ret = false;
if (rx.state >= FSM_SIG_STABLE) {
rx.state = FSM_WAIT_CLK_STABLE;
hdmirx_output_en(false);
@@ -2279,17 +2283,27 @@ int rx_set_port_hpd(u8 port_id, bool val)
if (port_id < E_PORT_NUM) {
if (val) {
hdmirx_wr_bits_top(TOP_HPD_PWR5V, _BIT(port_id), 1);
if (port_id == rx.port)
hdmirx_wr_bits_top(TOP_PORT_SEL, _BIT(port_id), 1);
hdmirx_wr_bits_top(TOP_PORT_SEL, _BIT(4), 1);
rx_set_term_value(port_id, 1);
} else {
hdmirx_wr_bits_top(TOP_HPD_PWR5V, _BIT(port_id), 0);
hdmirx_wr_bits_top(TOP_PORT_SEL, _BIT(4), 0);
if (port_id == rx.port)
hdmirx_wr_bits_top(TOP_PORT_SEL, _BIT(port_id), 0);
rx_set_term_value(port_id, 0);
}
} else if (port_id == ALL_PORTS) {
if (val) {
hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0xF);
if (port_id == rx.port)
hdmirx_wr_bits_top(TOP_PORT_SEL, _BIT(port_id), 1);
hdmirx_wr_bits_top(TOP_PORT_SEL, _BIT(4), 1);
rx_set_term_value(port_id, 1);
} else {
hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0x0);
hdmirx_wr_top(TOP_PORT_SEL, 0);
rx_set_term_value(port_id, 0);
}
} else {
@@ -2460,7 +2474,7 @@ bool rx_get_dig_clk_en_sts(void)
return ret;
}
void rx_esm_tmdsclk_en(bool en)
void rx_esm_tmds_clk_en(bool en)
{
if (rx.chip_id >= CHIP_ID_T7)
return;
@@ -2503,15 +2517,15 @@ void hdcp22_clk_en(bool en)
wr_reg_hhi(HHI_HDCP22_CLK_CNTL, data32);
/* axi clk config*/
if (rx.chip_id >= CHIP_ID_T5)
data32 = rd_reg_clk_ctl(HHI_AXI_CLK_CTNL);
data32 = rd_reg_clk_ctl(HHI_AXI_CLK_CNTL);
else
data32 = rd_reg_hhi(HHI_AXI_CLK_CTNL);
data32 = rd_reg_hhi(HHI_AXI_CLK_CNTL);
/* [ 8] clk_en. Enable gated clock */
data32 |= 1 << 8;
if (rx.chip_id >= CHIP_ID_T5)
wr_reg_clk_ctl(HHI_AXI_CLK_CTNL, data32);
wr_reg_clk_ctl(HHI_AXI_CLK_CNTL, data32);
else
wr_reg_hhi(HHI_AXI_CLK_CTNL, data32);
wr_reg_hhi(HHI_AXI_CLK_CNTL, data32);
if (rx.chip_id >= CHIP_ID_TL1)
/* TL1:esm related clk bit9-11 */
@@ -2529,10 +2543,10 @@ void hdcp22_clk_en(bool en)
} else {
if (rx.chip_id >= CHIP_ID_T5) {
wr_reg_clk_ctl(HHI_HDCP22_CLK_CNTL, 0);
wr_reg_clk_ctl(HHI_AXI_CLK_CTNL, 0);
wr_reg_clk_ctl(HHI_AXI_CLK_CNTL, 0);
} else {
wr_reg_hhi(HHI_HDCP22_CLK_CNTL, 0);
wr_reg_hhi(HHI_AXI_CLK_CTNL, 0);
wr_reg_hhi(HHI_AXI_CLK_CNTL, 0);
}
if (rx.chip_id >= CHIP_ID_TL1)
/* TL1:esm related clk bit9-11 */
@@ -2652,17 +2666,17 @@ void hdcp_22_on(void)
} else {
hdcp22_kill_esm = 0;
/* switch_set_state(&rx.hpd_sdev, 0x0); */
/* extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 0); */
/* extcon_set_state_sync(rx.rx_extcon_rx22, EXTCON_DISP_HDMI, 0); */
rx_hdcp22_send_uevent(0);
hdcp22_clk_en(1);
hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x1000);
/* rx_hdcp22_wr_top(TOP_SKP_CNTL_STAT, 0x1); */
/* hdmirx_hw_config(); */
/* switch_set_state(&rx.hpd_sdev, 0x1); */
/* extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 1); */
/* extcon_set_state_sync(rx.rx_extcon_rx22, EXTCON_DISP_HDMI, 1); */
rx_hdcp22_send_uevent(1);
hpd_to_esm = 1;
/* dont need to delay 900ms to wait sysctl start hdcp_rx22,*/
/* don't need to delay 900ms to wait sysctl start hdcp_rx22,*/
/*sysctl is userspace it wakes up later than driver */
/* mdelay(900); */
/* rx_set_cur_hpd(1); */
@@ -2762,19 +2776,19 @@ void clk_init_dwc(void)
data32 |= (0 << 4);
data32 |= (0 << 0);
if (rx.chip_id >= CHIP_ID_T5) {
wr_reg_clk_ctl(HHI_AUDPLL_CLK_OUT_CNTL, data32);
wr_reg_clk_ctl(HHI_AUD_PLL_CLK_OUT_CNTL, data32);
data32 |= (1 << 4);
wr_reg_clk_ctl(HHI_AUDPLL_CLK_OUT_CNTL, data32);
wr_reg_clk_ctl(HHI_AUD_PLL_CLK_OUT_CNTL, data32);
} else {
wr_reg_hhi(HHI_AUDPLL_CLK_OUT_CNTL, data32);
wr_reg_hhi(HHI_AUD_PLL_CLK_OUT_CNTL, data32);
data32 |= (1 << 4);
wr_reg_hhi(HHI_AUDPLL_CLK_OUT_CNTL, data32);
wr_reg_hhi(HHI_AUD_PLL_CLK_OUT_CNTL, data32);
}
}
data32 = hdmirx_rd_top(TOP_CLK_CNTL);
data32 |= 0 << 31; /* [31] disable clkgating */
data32 |= 1 << 17; /* [17] audfifo_rd_en */
data32 |= 1 << 16; /* [16] pktfifo_rd_en */
data32 |= 0 << 31; /* [31] disable clk_gating */
data32 |= 1 << 17; /* [17] aud_fifo_rd_en */
data32 |= 1 << 16; /* [16] pkt_fifo_rd_en */
if (rx.chip_id >= CHIP_ID_TL1) {
data32 |= 0 << 8; /* [8] tmds_ch2_clk_inv */
data32 |= 0 << 7; /* [7] tmds_ch1_clk_inv */
@@ -2783,7 +2797,7 @@ void clk_init_dwc(void)
data32 |= 0 << 4; /* [4] force_pll4x */
data32 |= 0 << 3; /* [3] phy_clk_inv: 1-invert */
} else {
data32 |= 1 << 2; /* [2] hdmirx_cecclk_en */
data32 |= 1 << 2; /* [2] hdmirx_cec_clk_en */
data32 |= 0 << 1; /* [1] bus_clk_inv */
data32 |= 0 << 0; /* [0] hdmi_clk_inv */
}
@@ -2837,7 +2851,7 @@ void hdmirx_20_init(void)
data32 |= 1 << 24; /* [25:24] i2c_spike_suppr */
data32 |= 0 << 20; /* [20] i2c_timeout_en */
data32 |= 0 << 0; /* [19:0] i2c_timeout_cnt */
hdmirx_wr_dwc(DWC_SCDC_I2CCONFIG, data32);
hdmirx_wr_dwc(DWC_SCDC_I2C_CONFIG, data32);
data32 = 0;
data32 |= 1 << 1; /* [1] hpd_low */
@@ -2851,7 +2865,7 @@ void hdmirx_20_init(void)
data32 = 0;
data32 |= 10 << 20; /* [29:20] chlock_max_err */
data32 |= 24000 << 0; /* [15:0] milisec_timer_limit */
data32 |= 24000 << 0; /* [15:0] mili_sec_timer_limit */
hdmirx_wr_dwc(DWC_CHLOCK_CONFIG, data32);
/* hdcp2.2 ctl */
@@ -2910,7 +2924,7 @@ int hdmirx_audio_init(void)
hdmirx_wr_dwc(DWC_AUD_CHEXTR_CTRL, data32);
data32 = 0;
/* [22:21] aport_shdw_ctrl */
/* [22:21] a port_sh_dw_ctrl */
data32 |= 3 << 21;
/* [20:19] auto_aclk_mute */
data32 |= auto_aclk_mute << 19;
@@ -2922,7 +2936,7 @@ int hdmirx_audio_init(void)
data32 |= aud_mute_sel << 5;
/* [4:3] aud_mute_mode */
data32 |= 1 << 3;
/* [2:1] aud_ttone_fs_sel */
/* [2:1] aud_t_tone_fs_sel */
data32 |= 0 << 1;
/* [0] testtone_en */
data32 |= 0 << 0;
@@ -3058,7 +3072,7 @@ void snps_phyg3_init(void)
/* NOTE!!!!! don't remove below setting */
hdmirx_wr_phy(OVL_PROT_CTRL, 0xa);
/* clear clkrate cfg */
/* clear clk_rate cfg */
hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT, CLK_RATE_BIT, 0);
/*last_clk_rate = 0;*/
rx.phy.clk_rate = 0;
@@ -3109,7 +3123,7 @@ void aml_phy_offset_cal(void)
* detect SCDC tmds clk ratio changes and
* update phy setting
*/
bool rx_clkrate_monitor(void)
bool rx_clk_rate_monitor(void)
{
u32 clk_rate, phy_band, pll_band;
bool changed = false;
@@ -3212,11 +3226,20 @@ void rx_hdcp_monitor(void)
return;
if (rx.hdcp.hdcp_version == HDCP_VER_NONE)
return;
if (rx.state != FSM_SIG_READY)
if (rx.state < FSM_SIG_STABLE)
return;
rx_get_ecc_info();
if (rx.ecc_err && rx.ecc_pkt_cnt == rx.ecc_err) {
if (log_level & VIDEO_LOG)
rx_pr("ecc:%d-%d\n", rx.ecc_err,
rx.ecc_pkt_cnt);
skip_frame(1);
rx.ecc_err_frames_cnt++;
} else {
rx.ecc_err_frames_cnt = 0;
}
if (rx.ecc_err_frames_cnt >= rx_ecc_err_frames) {
skip_frame(5);
if (rx.hdcp.hdcp_version == HDCP_VER_22)
rx_hdcp_22_sent_reauth();
else if (rx.hdcp.hdcp_version == HDCP_VER_14)
@@ -3374,20 +3397,20 @@ void rx_esm_reset(int level)
* not miss 2.2 interaction
*/
/* else */
/* rx_esm_tmdsclk_en(false); */
/* rx_esm_tmds_clk_en(false); */
} else if (level == 1) {//for open port
esm_set_stable(false);
esm_set_reset(true);
if (esm_recovery_mode == ESM_REC_MODE_TMDS)
rx_esm_tmdsclk_en(false);
rx_esm_tmds_clk_en(false);
} else if (level == 2) {//for fsm_restart&signal_status_init
if (esm_recovery_mode == ESM_REC_MODE_TMDS)
rx_esm_tmdsclk_en(false);
rx_esm_tmds_clk_en(false);
esm_set_stable(false);
} else if (level == 3) {//for dwc_reset
if (rx.hdcp.hdcp_version != HDCP_VER_14) {
if (esm_recovery_mode == ESM_REC_MODE_TMDS)
rx_esm_tmdsclk_en(true);
rx_esm_tmds_clk_en(true);
esm_set_stable(true);
if (rx.hdcp.hdcp_version == HDCP_VER_22)
hdmirx_hdcp22_reauth();
@@ -3459,12 +3482,12 @@ void cor_init(void)
data8 = 0;
data8 |= (0 << 6);//[7:6] reg_pp_status
data8 |= (1 << 5);//[5] reg_offset_coen
data8 |= (0 << 4);//[4] rerg_dc_ctl_ow //!!!!
data8 |= (0 << 4);//[4] reg_dc_ctl_ow //!!!!
data8 |= (0 << 0);//[3:0] reg_dc_ctl deep-color clock from the TMDS RX core
hdmirx_wr_cor(RX_TMDS_CCTRL2, data8);//register address: 0x1013
data8 = 0;
data8 |= (1 << 7);//reg_tst_xclk 1:Crystal oscillator clock muxed to test output pin
data8 |= (1 << 7);//reg_tst_x_clk 1:Crystal oscillator clock muxed to test output pin
data8 |= (0 << 6);//reg_tst_ckdt 1:CKDT muxed to test output pin
data8 |= (0 << 5);//reg_invert_tclk
hdmirx_wr_cor(RX_TEST_STAT, data8);//register address: 0x103b (0x80)
@@ -3566,7 +3589,7 @@ void cor_init(void)
hdmirx_wr_cor(RX_ACR_CTRL1_AUD_IVCRX, data8);//register address: 0x1400 (0x7a)
data8 = 0;
data8 |= (0 << 6);//[7:6] rhdmi_aud_sample_f_extn
data8 |= (0 << 6);//[7:6] r_hdmi_aud_sample_f_extn
data8 |= (0 << 4);//[4] reg_fs_filter_en
data8 |= (0 << 0);//[3:0] rhdmi_aud_sample_f
hdmirx_wr_cor(RX_TCLK_FS_AUD_IVCRX, data8); //register address: 0x1417 (0x0)
@@ -4268,6 +4291,15 @@ void rx_get_de_sts(void)
}
}
void rx_get_ecc_info(void)
{
if (rx.chip_id < CHIP_ID_T7)
return;
rx.ecc_err = rx_get_ecc_err();
rx.ecc_pkt_cnt = rx_get_ecc_pkt_cnt();
}
/*
* rx_get_video_info - get current avi info
*/
@@ -4379,7 +4411,7 @@ void hdmirx_config_video(void)
{
u32 temp = 0;
u8 data8;
u8 pixel_rpt_cnt;
int reg_clk_vp_core_div, reg_clk_vp_out_div;
if (dbg_cs & 0x10)
temp = dbg_cs & 0x0f;
@@ -4403,14 +4435,18 @@ void hdmirx_config_video(void)
case 1:
reg_clk_vp_core_div = 3;
reg_clk_vp_out_div = 1;
pixel_rpt_cnt = 1;
break;
case 3:
reg_clk_vp_core_div = 7;
reg_clk_vp_out_div = 3;
pixel_rpt_cnt = 2;
break;
case 7: //todo
default:
reg_clk_vp_core_div = 1;
reg_clk_vp_out_div = 0;
pixel_rpt_cnt = 0;
break;
}
data8 = hdmirx_rd_cor(RX_PWD0_CLK_DIV_0);
@@ -4424,7 +4460,7 @@ void hdmirx_config_video(void)
data8 = hdmirx_rd_cor(RX_VP_INPUT_FORMAT_HI);
data8 &= (~0x7);
data8 |= ((rx.cur.repeat & 0x3) << 0);
data8 |= ((pixel_rpt_cnt & 0x3) << 0);
hdmirx_wr_cor(RX_VP_INPUT_FORMAT_HI, data8);
}
rx_sw_reset_t7(2);
@@ -4469,7 +4505,7 @@ int rx_get_clock(enum measure_clk_top_e clk_src)
u32 tmp_data = 0;
u32 meas_cycles = 0;
u64 tmp_data2 = 0;
u64 audclk = 0;
u64 aud_clk = 0;
if (clk_src == TOP_HDMI_TMDSCLK) {
tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT);
@@ -4489,13 +4525,13 @@ int rx_get_clock(enum measure_clk_top_e clk_src)
/*get audio clk*/
tmp_data = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT0);
tmp_data2 = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT1);
audclk = ((tmp_data2 & 0xffff) << 32) | tmp_data;
aud_clk = ((tmp_data2 & 0xffff) << 32) | tmp_data;
if (tmp_data2 & (0x1 << 17))
audclk = div_u64((24000 * 65536), div_u64((audclk + 1), 1000));
aud_clk = div_u64((24000 * 65536), div_u64((aud_clk + 1), 1000));
else
rx_pr("audio clk measure fail\n");
}
clock = audclk;
clock = aud_clk;
} else {
tmp_data = 0;
}
@@ -4566,7 +4602,7 @@ void rx_clkmsr_handler(struct work_struct *work)
/*
* function - get clk related with hdmirx
*/
unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
unsigned int rx_measure_clock(enum measure_clk_src_e clk_src)
{
unsigned int clock = 0;
@@ -4599,16 +4635,16 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
* mpll clock [67] hdmirx_apll_clk_audio
* esm clock [68] Cts_hdcp22_esm
*/
if (clksrc == MEASURE_CLK_CABLE) {
if (clk_src == MEASURE_CLK_CABLE) {
if (rx.chip_id >= CHIP_ID_TL1 &&
rx.chip_id <= CHIP_ID_T5D) {
clock = meson_clk_measure(30);
/*clock = rx_get_clock(TOP_HDMI_CABLECLK);*/
/*clock = rx_get_clock(TOP_HDMI_CABLE_CLK);*/
} else if (rx.chip_id >= CHIP_ID_T7) {
clock = meson_clk_measure(44);
/*clock = rx_get_clock(TOP_HDMI_CABLECLK);*/
/*clock = rx_get_clock(TOP_HDMI_CABLE_CLK);*/
}
} else if (clksrc == MEASURE_CLK_TMDS) {
} else if (clk_src == MEASURE_CLK_TMDS) {
if (rx.chip_id >= CHIP_ID_TL1 &&
rx.chip_id <= CHIP_ID_T5D) {
clock = meson_clk_measure(63);
@@ -4621,28 +4657,28 @@ unsigned int rx_measure_clock(enum measure_clk_src_e clksrc)
clock = clock * 158000 / 4095 * 1000;
}
}
} else if (clksrc == MEASURE_CLK_PIXEL) {
} else if (clk_src == MEASURE_CLK_PIXEL) {
if (rx.chip_id >= CHIP_ID_T7)
clock = 1;
else
clock = meson_clk_measure(29);
} else if (clksrc == MEASURE_CLK_AUD_PLL) {
} else if (clk_src == MEASURE_CLK_AUD_PLL) {
if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(104);/*audio vid out*/
else
clock = meson_clk_measure(24);
} else if (clksrc == MEASURE_CLK_AUD_DIV) {
} else if (clk_src == MEASURE_CLK_AUD_DIV) {
if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(67);/*apll_clk_audio*/
else
clock = meson_clk_measure(98);
} else if (clksrc == MEASURE_CLK_MPLL) {
} else if (clk_src == MEASURE_CLK_MPLL) {
if (rx.chip_id >= CHIP_ID_TL1)
clock = 2;//meson_clk_measure(29);/*apll_clk_out_div*/
else
clock = meson_clk_measure(27);
} else if (clksrc == MEASURE_CLK_PCLK) {
} else if (clk_src == MEASURE_CLK_PCLK) {
clock = meson_clk_measure(0);
}
return clock;
@@ -4710,7 +4746,7 @@ void rx_debug_load22key(void)
msleep(20);
}
hdcp22_kill_esm = 0;
/* extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 0); */
/* extcon_set_state_sync(rx.rx_extcon_rx22, EXTCON_DISP_HDMI, 0); */
rx_hdcp22_send_uevent(0);
hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x0);
/* if key_a is already exist on platform,*/
@@ -4723,7 +4759,7 @@ void rx_debug_load22key(void)
hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x1000);
/* rx_hdcp22_wr_top(TOP_SKP_CNTL_STAT, 0x1); */
hdcp22_clk_en(1);
/* extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 1); */
/* extcon_set_state_sync(rx.rx_extcon_rx22, EXTCON_DISP_HDMI, 1); */
rx_hdcp22_send_uevent(1);
mdelay(100);
hdmi_rx_top_edid_update();
@@ -5048,18 +5084,18 @@ int rx_get_aud_pll_err_sts(void)
return ret;
}
u32 aml_cable_clk_band(u32 cableclk, u32 clkrate)
u32 aml_cable_clk_band(u32 cable_clk, u32 clk_rate)
{
u32 bw;
u32 cab_clk = cableclk;
u32 cab_clk = cable_clk;
if (rx.chip_id < CHIP_ID_TL1)
return PHY_BW_2;
/* rx_pr("cable clk=%d, clkrate=%d\n", cableclk, clkrate); */
/* rx_pr("cable clk=%d, clk_rate=%d\n", cable_clk, clk_rate); */
/* 1:40 */
if (clkrate)
cab_clk = cableclk << 2;
if (clk_rate)
cab_clk = cable_clk << 2;
/* 1:10 */
if (rx.chip_id == CHIP_ID_T5M) {
@@ -5096,13 +5132,13 @@ u32 aml_cable_clk_band(u32 cableclk, u32 clkrate)
return bw;
}
u32 aml_phy_pll_band(u32 cableclk, u32 clkrate)
u32 aml_phy_pll_band(u32 cable_clk, u32 clk_rate)
{
u32 bw;
u32 cab_clk = cableclk;
u32 cab_clk = cable_clk;
if (clkrate)
cab_clk = cableclk << 2;
if (clk_rate)
cab_clk = cable_clk << 2;
/* 1:10 */
if (rx.chip_id == CHIP_ID_T5M) {
@@ -5254,17 +5290,17 @@ void rx_get_best_eq_setting(void)
bool is_tmds_clk_stable(void)
{
bool ret = true;
u32 cableclk;
u32 cable_clk;
if (rx.phy.clk_rate)
cableclk = rx.clk.cable_clk * 4;
cable_clk = rx.clk.cable_clk * 4;
else
cableclk = rx.clk.cable_clk;
cable_clk = rx.clk.cable_clk;
if (abs(cableclk - rx.clk.tmds_clk) > clock_lock_th * MHz) {
if (abs(cable_clk - rx.clk.tmds_clk) > clock_lock_th * MHz) {
if (log_level & VIDEO_LOG)
rx_pr("cableclk=%d,tmdsclk=%d,\n",
cableclk / MHz, rx.clk.tmds_clk / MHz);
rx_pr("cable_clk=%d,tmdsclk=%d,\n",
cable_clk / MHz, rx.clk.tmds_clk / MHz);
ret = false;
} else {
ret = true;
@@ -5274,7 +5310,7 @@ bool is_tmds_clk_stable(void)
void aml_phy_init_handler(struct work_struct *work)
{
//cancel_work(&amlphy_dwork);
//cancel_work(&aml_phy_dwork);
if (rx.phy_ver == PHY_VER_TL1)
aml_phy_init_tl1();
else if (rx.phy_ver == PHY_VER_TM2)
@@ -5292,7 +5328,7 @@ void aml_phy_init_handler(struct work_struct *work)
void aml_phy_init(void)
{
schedule_work(&amlphy_dwork);
schedule_work(&aml_phy_dwork);
eq_sts = E_EQ_START;
}
@@ -5475,9 +5511,17 @@ void rx_emp_to_ddr_init(void)
data32 |= 0 << 22; /* ddr_store_drm */
else
data32 |= 1 << 22;/* ddr_store_drm */
data32 |= 1 << 19;/* ddr_store_aif */
/* ddr_store_aif */
if (rx.chip_id == CHIP_ID_T7)
data32 |= 1 << 19;
else
data32 |= 0 << 19;
data32 |= 0 << 18;/* ddr_store_spd */
#ifdef MULTI_VSIF_EXPORT_TO_EMP
data32 |= 1 << 16;/* ddr_store_vsi */
#else
data32 |= 0 << 16;/* ddr_store_vsi */
#endif
data32 |= 1 << 15;/* ddr_store_emp */
data32 |= 0 << 12;/* ddr_store_amp */
data32 |= 0 << 8;/* ddr_store_hbr */
@@ -5526,7 +5570,7 @@ void rx_emp_field_done_irq(void)
unsigned char *src_addr = 0;
unsigned char *dst_addr;
unsigned int i, j, k;
unsigned int datacnt = 0;
unsigned int data_cnt = 0;
struct page *cur_start_pg_addr;
/*emp data start physical address*/
@@ -5550,7 +5594,8 @@ void rx_emp_field_done_irq(void)
recv_pkt_cnt = EMP_BUFF_MAX_PKT_CNT - 1;
rx_pr("pkt cnt err:%d\n", recv_pkt_cnt);
}
if (!rx.emp_pkt_rev)
rx.emp_pkt_rev = true;
for (i = 0; i < recv_pagenum;) {
/*one page 4k*/
cur_start_pg_addr = phys_to_page(p_addr + i * PAGE_SIZE);
@@ -5563,8 +5608,8 @@ void rx_emp_field_done_irq(void)
emp_pkt_cnt++;
/*32 bytes per emp pkt*/
for (k = 0; k < 32; k++) {
dst_addr[datacnt] = src_addr[j + k];
datacnt++;
dst_addr[data_cnt] = src_addr[j + k];
data_cnt++;
}
//}
j += 32;
@@ -5576,8 +5621,8 @@ void rx_emp_field_done_irq(void)
emp_pkt_cnt++;
/*32 bytes per emp pkt*/
for (k = 0; k < 32; k++) {
dst_addr[datacnt] = src_addr[j + k];
datacnt++;
dst_addr[data_cnt] = src_addr[j + k];
data_cnt++;
}
//}
j += 32;
@@ -5835,7 +5880,7 @@ todo:
}
/*
* for Nvdia PC long detection time issue
* for Nvidia PC long detection time issue
*/
void rx_i2c_err_monitor(void)
{
@@ -5867,6 +5912,19 @@ bool is_ddc_filter_en(void)
return ret;
}
bool rx_need_ddc_monitor(void)
{
bool ret = true;
if (ddc_dbg_en)
ret = false;
if (rx.chip_id > CHIP_ID_T5W || (is_meson_t7_cpu() && is_meson_rev_c()))
ret = false;
return ret;
}
/*
* FUNC: rx_ddc_active_monitor
* ddc active monitor
@@ -5874,8 +5932,8 @@ bool is_ddc_filter_en(void)
void rx_ddc_active_monitor(void)
{
u32 temp = 0;
/*check the version of t7*/
if (ddc_dbg_en || !is_t7_former())
if (!rx_need_ddc_monitor())
return;
if (rx.state != FSM_WAIT_CLK_STABLE)
@@ -5910,8 +5968,17 @@ void rx_ddc_active_monitor(void)
*0x13 for 8268 refer to 73940
*fix edid filter setting
*/
if (temp < 0x3f && temp != 1 && temp != 8 && temp != 0x0c && temp != 0x0a &&
temp != 0x15 && temp != 0x14 && temp != 0x13 && temp) {
if (temp < 0x3f &&
temp != 0x1 &&
temp != 0x2 &&
temp != 0x3 &&
temp != 0x8 &&
temp != 0xa &&
temp != 0xc &&
temp != 0x13 &&
temp != 0x14 &&
temp != 0x15 &&
temp) {
rx.ddc_filter_en = true;
if (log_level & EDID_LOG)
rx_pr("port: %d, edid_status: 0x%x,\n", rx.port, temp);
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h
+17 -19
View File
@@ -25,7 +25,7 @@
#define MODET_CLK_EN _BIT(24)
#define CFG_CLK_EN _BIT(8)
#define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x1081 */
#define HHI_AXI_CLK_CTNL (0xb8 * 4)
#define HHI_AXI_CLK_CNTL (0xb8 * 4)
#define HHI_VDAC_CNTL0 (0xbb * 4)
#define HHI_VDAC_CNTL1 (0xbc * 4)
#define HHI_AUD_PLL_CNTL (0xf8 * 4)
@@ -55,7 +55,7 @@
/* TXLX */
/* unified_register.h by wujun */
#define HHI_AUDPLL_CLK_OUT_CNTL (0x8c << 2)
#define HHI_AUD_PLL_CLK_OUT_CNTL (0x8c << 2)
#define HHI_VDAC_CNTL0_TXLX (0xBD * 4)
#define PREG_PAD_GPIO0_EN_N (0x0c * 4)
#define PREG_PAD_GPIO0_O (0x0d * 4)
@@ -231,7 +231,7 @@
#define TOP_METER_CABLE_STAT 0x03b
#define TOP_CHAN_SWITCH_1 0x03c
/* tl1 */
#define TOP_AUDPLL_LOCK_FILTER 0x040
#define TOP_AUD_PLL_LOCK_FILTER 0x040
/* tl1 */
#define TOP_CHAN01_ERRCNT 0x041
@@ -428,7 +428,7 @@
/* HDMI 2.0 feature registers */
/* bit0-1 scramble ctrl */
#define DWC_HDMI20_CONTROL 0x0800
#define DWC_SCDC_I2CCONFIG 0x0804
#define DWC_SCDC_I2C_CONFIG 0x0804
#define DWC_SCDC_CONFIG 0x0808
#define DWC_CHLOCK_CONFIG 0x080C
#define DWC_HDCP22_CONTROL 0x081C
@@ -661,7 +661,7 @@
/*tl1*/
#define PFIFO_EMP_EN _BIT(30)/*type:0x7f*/
#define GCP_GLOBAVMUTE _BIT(15)
#define GCP_GLOB_AVMUTE _BIT(15)
/** Packet FIFO clear min/max information */
#define PD_FIFO_FILL_INFO_CLR _BIT(8)
/** Packet FIFO skip one packet */
@@ -1087,11 +1087,9 @@
#define HHI_HDMIRX_PHY_MISC_CNTL1 (0xd8 << 2)
#define MISCI_MANUAL_MODE _BIT(22)
#define HHI_HDMIRX_PHY_MISC_CNTL2 (0xe0 << 2)
/*[4:5] in trim,[6:7] im trim*/
#define HHI_HDMIRX_PHY_DCHD_CNTL0 (0xe5 << 2)
#define HHI_HDMIRX_PHY_DCHD_CNTL1 (0xe6 << 2)
#define HHI_HDMIRX_PHY_ARC_CNTL (0xe8 << 2)
#define HHI_HDMIRX_EARCTX_CNTL0 (0x69 << 2)
#define HHI_HDMIRX_EARCTX_CNTL1 (0x6a << 2)
@@ -1099,7 +1097,9 @@
#define HHI_HDMIRX_PHY_DCHD_STAT (0xef << 2)
/* T5 HIU apll register */
/* T5 HIU PHY register */
/* T7 HIU PHY register */
#define TMDS_CLK_MIN (15000UL)
#define TMDS_CLK_MAX (340000UL)
@@ -1154,7 +1154,7 @@
#define COR_CTS_LO 0x140C
#define COR_CTS_MI 0x140D
#define COR_CTS_HI 0x140E
/* h-ative (pixel per line) */
/* h-active (pixel per line) */
#define COR_PIXEL_CNT_LO 0x188C
#define COR_PIXEL_CNT_HI 0x188D
#define COR_LINE_CNT_LO 0x188E
@@ -2415,7 +2415,7 @@
#define VP_VTG_VACTIVE_VIDEO_END_VID_IVCRX 0x00001876
#define VP_VTG_VEND_OF_FRAME_VID_IVCRX 0x00001878
#define VP_VTG_CFG_VID_IVCRX 0x0000187a
#define VP_VTG_THREHOLD_VID_IVCRX 0x0000187b
#define VP_VTG_THRESHOLD_VID_IVCRX 0x0000187b
#define VP_VTG_CYCLE_DELAY_VID_IVCRX 0x0000187c
#define VP_VTG_UPDATE_REQUEST_VID_IVCRX 0x0000187e
#define VP_VTG_BANK_CFG_VID_IVCRX 0x0000187f
@@ -2457,7 +2457,7 @@
#define VP_EMBD_SYNC_ENC_HBLANKING_PIXELS_VID_IVCRX 0x000018de
#define VP_EMBD_SYNC_ENC_UPDATE_REQUEST_VID_IVCRX 0x000018e0
#define VP_EMBD_SYNC_ENC_BANC_CFG_VID_IVCRX 0x000018e1
#define VP_FRMAES_CNT_VID_IVCRX 0x000018e4
#define VP_FRAMES_CNT_VID_IVCRX 0x000018e4
#define VP_PIXEL_CLK_CNT_VID_IVCRX 0x000018e8
#define VP_INTERLACE_FIELD_VID_IVCRX 0x000018ec
@@ -3100,6 +3100,7 @@ extern int phy_term_lel;
extern bool phy_tdr_en;
extern int hdcp_tee_path;
extern char emp_buf[1024];
extern char pre_emp_buf[1024];
extern int hdcp22_on;
extern int hdcp14_on;
extern int hdcp22_kill_esm;
@@ -3206,8 +3207,8 @@ void hdmirx_set_video_mute(bool mute);
void hdmirx_config_video(void);
void hdmirx_config_audio(void);
void set_dv_ll_mode(bool en);
void rx_get_audinfo(struct aud_info_s *audio_info);
bool rx_clkrate_monitor(void);
void rx_get_aud_info(struct aud_info_s *audio_info);
bool rx_clk_rate_monitor(void);
void rx_ddc_calibration(bool en);
unsigned char rx_get_hdcp14_sts(void);
unsigned int rx_hdcp22_rd_reg_bits(unsigned int addr, unsigned int mask);
@@ -3267,10 +3268,6 @@ void rx_dig_clk_en(bool en);
void dump_reg_phy_tl1_tm2(void);
void aml_phy_get_trim_val_tl1_tm2(void);
/* tm2 extern */
/* t5 extern */
void hdmirx_wr_bits_amlphy(unsigned int addr,
unsigned int mask,
unsigned int value);
@@ -3280,16 +3277,17 @@ unsigned int hdmirx_rd_amlphy(unsigned int addr);
void hdmirx_irq_hdcp_enable(bool enable);
u8 rx_get_avmute_sts(void);
/* T7 */
u8 hdmirx_rd_cor(u32 addr);
void hdmirx_wr_cor(u32 addr, u8 data);
u8 hdmirx_rd_bits_cor(u32 addr, u32 mask);
void hdmirx_wr_bits_cor(u32 addr, u32 mask, u8 value);
void rx_hdcp_22_sent_reauth(void);
void rx_hdcp_14_sent_reauth(void);
u32 rx_get_ecc_err(void);
u32 rx_get_ecc_pkt_cnt(void);
void rx_check_ecc_error(void);
//void rx_check_ecc_error(void);
void rx_get_ecc_info(void);
void hdmirx_output_en(bool en);
void hdmirx_hbr2spdif(u8 val);
void rx_hdcp_monitor(void);
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c
+1 -1
View File
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
*/
#include <linux/version.h>
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.h
+1 -1
View File
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
*/
#ifndef _HDMI_RX_T3X_H
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t5.c
+13 -7
View File
@@ -859,11 +859,17 @@ void aml_phy_get_trim_val_t5(void)
{
u32 data32;
data32 = hdmirx_rd_amlphy(T5_HHI_RX_PHY_MISC_CNTL1);
/* bit [12: 15]*/
rterm_trim_val_t5 = (data32 >> 12) & 0xf;
/* bit'0*/
rterm_trim_flag_t5 = data32 & 0x1;
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
if (dts_debug_flag == 0) {
data32 = hdmirx_rd_amlphy(T5_HHI_RX_PHY_MISC_CNTL1);
rterm_trim_val_t5 = (data32 >> 12) & 0xf;
rterm_trim_flag_t5 = data32 & 0x1;
} else {
rlevel = phy_term_lel & 0xf;
if (rlevel > 15)
rlevel = 15;
rterm_trim_flag_t5 = dts_debug_flag;
}
if (rterm_trim_flag_t5)
rx_pr("rterm trim=0x%x\n", rterm_trim_val_t5);
}
@@ -1255,7 +1261,7 @@ void dump_aml_phy_sts_t5(void)
sli1_ofst5 = (data32 >> 8) & 0x3f;
sli2_ofst5 = (data32 >> 16) & 0x3f;
rx_pr("\nhdmirx phy status:\n");
rx_pr("\n hdmirx phy status:\n");
rx_pr("pll_lock=%d, squelch=%d, terminal=%d\n", pll_lock, squelch, terminal);
rx_pr("vga_gain=[%d,%d,%d]\n",
ch0_vga, ch1_vga, ch2_vga);
@@ -1605,7 +1611,7 @@ int aml_phy_get_iq_skew_val_t5(u32 val_0, u32 val_1)
/* IQ skew monitor */
void aml_phy_iq_skew_monitor_t5(void)
{
int data32;
int data32;
int bist_mode = 3;
u32 cdr0_code_0, cdr0_code_1, cdr0_code_2;/*clk0*/
u32 cdr1_code_0, cdr1_code_1, cdr1_code_2;/*clk90*/
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t7.c
+15 -11
View File
@@ -903,11 +903,17 @@ void aml_phy_get_trim_val_t7(void)
{
u32 data32;
data32 = hdmirx_rd_amlphy(T7_HHI_RX_PHY_MISC_CNTL1);
/* bit [12: 15]*/
rterm_trim_val_t7 = (data32 >> 12) & 0xf;
/* bit'0*/
rterm_trim_flag_t7 = data32 & 0x1;
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
if (dts_debug_flag == 0) {
data32 = hdmirx_rd_amlphy(T7_HHI_RX_PHY_MISC_CNTL1);
rterm_trim_val_t7 = (data32 >> 12) & 0xf;
rterm_trim_flag_t7 = data32 & 0x1;
} else {
rlevel = phy_term_lel & 0xf;
if (rlevel > 15)
rlevel = 15;
rterm_trim_flag_t7 = dts_debug_flag;
}
if (rterm_trim_flag_t7)
rx_pr("rterm trim=0x%x\n", rterm_trim_val_t7);
}
@@ -1973,16 +1979,20 @@ void rx_set_irq_t7(bool en)
if (en) {
data8 = 0;
#ifndef MULTI_VSIF_EXPORT_TO_EMP
data8 |= 1 << 4; /* intr_new_unrec en */
data8 |= 1 << 2; /* intr_new_aud */
#endif
data8 |= 1 << 1; /* intr_spd */
hdmirx_wr_cor(RX_DEPACK_INTR2_MASK_DP2_IVCRX, data8);
#ifndef MULTI_VSIF_EXPORT_TO_EMP
data8 = 0;
data8 |= 1 << 4; /* intr_cea_repeat_hf_vsi en */
data8 |= 1 << 3; /* intr_cea_new_hf_vsi en */
data8 |= 1 << 2; /* intr_cea_new_vsi */
hdmirx_wr_cor(RX_DEPACK_INTR3_MASK_DP2_IVCRX, data8);
#endif
hdmirx_wr_cor(RX_GRP_INTR1_MASK_PWD_IVCRX, 0x25);
hdmirx_wr_cor(RX_INTR1_MASK_PWD_IVCRX, 0x03);//register_address: 0x1050
@@ -2359,9 +2369,3 @@ u8 rx_get_stream_manage_info(void)
__func__, k, stream_type_hi, stream_type_low);
return stream_type_low;
}
/*t7 version*/
int is_t7_former(void)
{
return (is_meson_t7_cpu() && (is_meson_rev_a() || is_meson_rev_b()));
}
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t7.h
+1 -1
View File
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
*/
#ifndef _HDMI_RX_T7_H
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_tl1.h
+1 -1
View File
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
*/
#ifndef _HDMI_RX_TL1_H
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_tm2.h
+1 -1
View File
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
*/
#ifndef _HDMI_RX_TM2_H
drivers/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c
+328 -67
View File
@@ -469,6 +469,10 @@ static void rx_pktdump_vsi(void *pdata)
struct vsi_infoframe_st *pktdata = pdata;
u32 i;
#ifdef MULTI_VSIF_EXPORT_TO_EMP
if (!pktdata->ieee)
return;
#endif
rx_pr(">---vsi infoframe detail -------->\n");
rx_pr("type: 0x%x\n", pktdata->pkttype);
rx_pr("ver: %d\n", pktdata->ver_st.version);
@@ -689,6 +693,9 @@ void rx_pkt_dump(enum pkt_type_e typeid)
{
struct packet_info_s *prx = &rx_pkt;
union infoframe_u pktdata;
#ifdef MULTI_VSIF_EXPORT_TO_EMP
int i;
#endif
rx_pr("dump cmd:0x%x\n", typeid);
@@ -697,11 +704,15 @@ void rx_pkt_dump(enum pkt_type_e typeid)
switch (typeid) {
/*infoframe pkt*/
case PKT_TYPE_INFOFRAME_VSI:
#ifndef MULTI_VSIF_EXPORT_TO_EMP
rx_pktdump_raw(&prx->vs_info);
rx_pktdump_vsi(&prx->vs_info);
rx_pr("-------->ex register set >>\n");
rx_pkt_get_vsi_ex(&pktdata);
rx_pktdump_vsi(&pktdata);
#else
for (i = 0; i < VSI_TYPE_MAX; i++)
rx_pktdump_vsi(&prx->multi_vs_info[i]);
#endif
break;
case PKT_TYPE_INFOFRAME_AVI:
rx_pktdump_raw(&prx->avi_info);
@@ -817,9 +828,16 @@ u32 rx_pkt_type_mapping(enum pkt_type_e pkt_type)
void rx_pkt_initial(void)
{
#ifdef MULTI_VSIF_EXPORT_TO_EMP
int i = 0;
while (i < VSI_TYPE_MAX)
memset(&rx_pkt.multi_vs_info[i++], 0, sizeof(struct pd_infoframe_s));
#else
memset(&rx_pkt.vs_info, 0, sizeof(struct pd_infoframe_s));
#endif
memset(&rxpktsts, 0, sizeof(struct rxpkt_st));
memset(&rx_pkt.vs_info, 0, sizeof(struct pd_infoframe_s));
memset(&rx_pkt.avi_info, 0, sizeof(struct pd_infoframe_s));
memset(&rx_pkt.spd_info, 0, sizeof(struct pd_infoframe_s));
memset(&rx_pkt.aud_pktinfo, 0, sizeof(struct pd_infoframe_s));
@@ -1081,9 +1099,9 @@ void rx_pkt_get_vsi_ex(void *pktinfo)
pkt->length = hdmirx_rd_cor(AUDRX_TYPE_DP2_IVCRX) & 0x1f;
pkt->ieee = IEEE_HDR10PLUS;
if (rx_vsif_type & VSIF_TYPE_HDMI21) {
tmp = hdmirx_rd_cor(RX_UNREC_BYTE9_DP2_IVCRX);
tmp = hdmirx_rd_cor(VSIRX_DBYTE5_DP3_IVCRX);
if ((tmp >> 1) & 1)
pkt->ieee = IEEE_DV_PLUS_ALLM;
pkt->ieee = IEEE_HDR10P_PLUS_ALLM;
}
for (i = 0; i < 24; i++) {
tmp = hdmirx_rd_cor(AUDRX_DBYTE4_DP2_IVCRX + i);
@@ -1352,8 +1370,10 @@ void rx_get_vsi_info(void)
rx.vs_info_details.hdmi_allm = false;
rx.vs_info_details.dolby_vision_flag = DV_NULL;
rx.vs_info_details.hdr10plus = false;
rx.vs_info_details.cuva_hdr = false;
rx.vs_info_details.emp_pkt_cnt = rx.emp_buff.emp_pkt_cnt;
rx.emp_buff.emp_pkt_cnt = 0;
#ifndef MULTI_VSIF_EXPORT_TO_EMP
pkt = (struct vsi_infoframe_st *)&rx_pkt.vs_info;
if (log_level & PACKET_LOG)
@@ -1438,6 +1458,20 @@ void rx_get_vsi_info(void)
/* consider hdr10+ is true when IEEE matched */
rx.vs_info_details.hdr10plus = true;
break;
case IEEE_HDR10P_PLUS_ALLM:
/* HDR10+ */
rx.vs_info_details.vsi_state = E_VSI_HDR10PLUS;
if (pkt->length != E_PKT_LENGTH_27 ||
pkt->pkttype != 0x01 ||
pkt->ver_st.version != 0x01 ||
((pkt->sbpkt.payload.data[1] >> 6) & 0x03) != 0x01)
if (log_level & PACKET_LOG)
rx_pr("vsi hdr10+ length err\n");
/* consider hdr10+ is true when IEEE matched */
rx.vs_info_details.hdr10plus = true;
rx.vs_info_details.hdmi_allm = true;
pkt->ieee = IEEE_HDR10PLUS;
break;
case IEEE_VSI14:
/* dolbyvision1.0 */
rx.vs_info_details.vsi_state = E_VSI_4K3D;
@@ -1470,6 +1504,99 @@ void rx_get_vsi_info(void)
default:
break;
}
#else
int i = 0;
while (i < VSI_TYPE_MAX) {
pkt = (struct vsi_infoframe_st *)&rx_pkt.multi_vs_info[i];
if ((log_level & PACKET_LOG) && pkt->ieee && rx.new_emp_pkt)
rx_pr("ieee[%d/%d]-%x\n", i, VSI_TYPE_MAX, pkt->ieee);
if (pkt->ieee == IEEE_DV15) {
/* dolbyvision 1.5 */
if (pkt->length != E_PKT_LENGTH_27) {
if (log_level & PACKET_LOG)
rx_pr("vsi dv15 length err\n");
//dv vsif
rx.vs_info_details.dolby_vision_flag = DV_VSIF;
i++;
continue;
}
tmp = pkt->sbpkt.payload.data[0] & _BIT(1);
if (tmp) {
rx.vs_info_details.dolby_vision_flag = DV_VSIF;
tmp = pkt->sbpkt.payload.data[0] & _BIT(0);
rx.vs_info_details.low_latency = tmp ? true : false;
tmp = pkt->sbpkt.payload.data[0] >> 15 & 0x01;
rx.vs_info_details.backlt_md_bit = tmp ? true : false;
if (tmp) {
tmp = (pkt->sbpkt.payload.data[0] >> 16 & 0xff) |
(pkt->sbpkt.payload.data[0] & 0xf00);
rx.vs_info_details.eff_tmax_pq = tmp;
}
tmp = (pkt->sbpkt.payload.data[1] >> 16 & 0xf);
if (tmp == 2)
rx.vs_info_details.dv_allm = true;
}
} else if (pkt->ieee == IEEE_HDR10PLUS) {
/* HDR10+ */
if (pkt->length != E_PKT_LENGTH_27 ||
pkt->pkttype != 0x01 ||
pkt->ver_st.version != 0x01 ||
((pkt->sbpkt.payload.data[1] >> 6) & 0x03) != 0x01)
if (log_level & PACKET_LOG)
rx_pr("vsi hdr10+ length err\n");
/* consider hdr10+ is true when IEEE matched */
rx.vs_info_details.hdr10plus = true;
rx.vs_info_details.dv_allm = true;
pkt->ieee = IEEE_HDR10PLUS;
} else if (pkt->ieee == IEEE_CUVAHDR) {
if (pkt->length != E_PKT_LENGTH_27) {
if (log_level & PACKET_LOG)
rx_pr("cuva hdr length err\n");
}
tmp = pkt->sbpkt.payload.data[0] & 0xff;
rx.vs_info_details.sys_start_code = tmp;
tmp = (pkt->sbpkt.payload.data[1] >> 4) & 0xf;
rx.vs_info_details.cuva_version_code = tmp;
pkt->sbpkt.vsi_cuva_hdr.transfer_char = 0;
pkt->sbpkt.vsi_cuva_hdr.monitor_mode_enable = 1;
rx.vs_info_details.cuva_hdr = true;
}
if (pkt->ieee == IEEE_VSI14) {
/* dolbyvision1.0 */
if (pkt->length == E_PKT_LENGTH_24) {
rx.vs_info_details.dolby_vision_flag = DV_VSIF;
if ((pkt->sbpkt.payload.data[0] & 0xffff) == 0)
pkt->sbpkt.payload.data[0] = 0xffff;
rx.vs_info_details.vsi_state = E_VSI_DV10;
} else if ((pkt->length == E_PKT_LENGTH_5) &&
(pkt->sbpkt.payload.data[0] & 0xffff)) {
rx.vs_info_details.dolby_vision_flag = DV_NULL;
} else if ((pkt->length == E_PKT_LENGTH_4) &&
((pkt->sbpkt.payload.data[0] & 0xff) == 0)) {
rx.vs_info_details.dolby_vision_flag = DV_NULL;
} else {
if (pkt->sbpkt.vsi_3dext.vdfmt == VSI_FORMAT_3D_FORMAT) {
rx.vs_info_details._3d_structure =
pkt->sbpkt.vsi_3dext.threed_st;
rx.vs_info_details._3d_ext_data =
pkt->sbpkt.vsi_3dext.threed_ex;
if (log_level & VSI_LOG)
rx_pr("struct_3d:%d, struct_3d_ext:%d\n",
pkt->sbpkt.vsi_3dext.threed_st,
pkt->sbpkt.vsi_3dext.threed_ex);
}
rx.vs_info_details.dolby_vision_flag = DV_NULL;
}
} else if (pkt->ieee == IEEE_VSI21) {
/* hdmi2.1 */
tmp = pkt->sbpkt.payload.data[0] & _BIT(9);
rx.vs_info_details.hdmi_allm = tmp ? true : false;
}
i++;
}
#endif
if (rx.vs_info_details.emp_pkt_cnt &&
rx.emp_buff.emp_tagid == IEEE_DV15) {
//pkt->ieee = rx.emp_buff.emp_tagid;
@@ -1494,15 +1621,24 @@ void rx_get_vsi_info(void)
rx.emp_buff.emp_tagid = 0;
/* pkt->ieee = 0; */
/* memset(&rx_pkt.vs_info, 0, sizeof(struct pd_infoframe_s)); */
}
}
void rx_pkt_buffclear(enum pkt_type_e pkt_type)
{
struct packet_info_s *prx = &rx_pkt;
void *pktinfo;
#ifdef MULTI_VSIF_EXPORT_TO_EMP
int i = 0;
#endif
if (pkt_type == PKT_TYPE_INFOFRAME_VSI) {
#ifdef MULTI_VSIF_EXPORT_TO_EMP
while (i < VSI_TYPE_MAX)
memset(&prx->multi_vs_info[i++], 0, sizeof(struct pd_infoframe_s));
return;
#else
pktinfo = &prx->vs_info;
#endif
} else if (pkt_type == PKT_TYPE_INFOFRAME_AVI) {
pktinfo = &prx->avi_info;
} else if (pkt_type == PKT_TYPE_INFOFRAME_SPD) {
@@ -1949,6 +2085,7 @@ int rx_pkt_fifodecode(struct packet_info_s *prx,
{
switch (pktdata->raw_infoframe.pkttype) {
case PKT_TYPE_INFOFRAME_VSI:
#ifndef MULTI_VSIF_EXPORT_TO_EMP
if (rxpktsts.dv_pkt_num > 0) {
if (!is_new_visf_pkt_rcv(pktdata))
break;
@@ -1960,6 +2097,39 @@ int rx_pkt_fifodecode(struct packet_info_s *prx,
pktsts->pkt_op_flag |= PKT_OP_VSI;
memcpy(&prx->vs_info, pktdata,
sizeof(struct pd_infoframe_s));
#else
if (log_level & PACKET_LOG && rx.new_emp_pkt)
rx_pr("ieee_type:0x%x\n", pktdata->vsi_infoframe.ieee);
switch (pktdata->vsi_infoframe.ieee) {
case IEEE_DV15:
memcpy(&prx->multi_vs_info[DV15], pktdata,
sizeof(struct pd_infoframe_s));
rx.vs_info_details.vsi_state |= E_VSI_DV15;
break;
case IEEE_HDR10PLUS:
memcpy(&prx->multi_vs_info[HDR10PLUS], pktdata,
sizeof(struct pd_infoframe_s));
rx.vs_info_details.vsi_state |= E_VSI_HDR10PLUS;
break;
case IEEE_CUVAHDR:
memcpy(&prx->multi_vs_info[CUVAHDR], pktdata,
sizeof(struct pd_infoframe_s));
rx.vs_info_details.vsi_state |= E_VSI_CUVAHDR;
break;
case IEEE_VSI21:
memcpy(&prx->multi_vs_info[VSI21], pktdata,
sizeof(struct pd_infoframe_s));
rx.vs_info_details.vsi_state |= E_VSI_VSI21;
break;
case IEEE_VSI14:
memcpy(&prx->multi_vs_info[VSI14], pktdata,
sizeof(struct pd_infoframe_s));
rx.vs_info_details.vsi_state |= E_VSI_4K3D;
break;
default:
break;
}
#endif
pktsts->pkt_op_flag &= ~PKT_OP_VSI;
break;
case PKT_TYPE_INFOFRAME_AVI:
@@ -2080,6 +2250,35 @@ int rx_pkt_fifodecode(struct packet_info_s *prx,
return 0;
}
static void rx_parse_dsf(unsigned char *src_addr)
{
bool first, last;
u8 sequence_index;
first = *(src_addr + 1) >> 7;
last = (*(src_addr + 1) >> 6) & 0x1;
sequence_index = *(src_addr + 2);
if (log_level & PACKET_LOG && rx.new_emp_pkt)
rx_pr("dst_addr:0x%x, dst_addr+1:0x%x, first:%d, last:%d\n",
*src_addr, *(src_addr + 1), first, last);
if (first)
rx.emp_dsf_info[rx.emp_dsf_cnt].pkt_addr = src_addr;
if (last) {
rx.emp_dsf_info[rx.emp_dsf_cnt].pkt_cnt = sequence_index + 1;
rx.emp_dsf_cnt++;
}
}
bool is_emp_buf_change(void)
{
if (rx.emp_buff.pre_emp_pkt_cnt != rx.emp_buff.emp_pkt_cnt)
return true;
else if (memcmp(emp_buf, pre_emp_buf, rx.emp_buff.emp_pkt_cnt * 32) != 0)
return true;
else
return false;
}
int rx_pkt_handler(enum pkt_decode_type pkt_int_src)
{
//u32 i = 0;
@@ -2093,6 +2292,8 @@ int rx_pkt_handler(enum pkt_decode_type pkt_int_src)
/*u32 t1, t2;*/
rxpktsts.dv_pkt_num = 0;
rxpktsts.fifo_pkt_num = 0;
if (log_level & PACKET_LOG)
rx_pr("pkt_int_src:0x%x\n", pkt_int_src);
if (pkt_int_src == PKT_BUFF_SET_FIFO) {
/*from pkt fifo*/
if (!pd_fifo_buf)
@@ -2181,11 +2382,22 @@ int rx_pkt_handler(enum pkt_decode_type pkt_int_src)
/*from pkt fifo*/
if (!pd_fifo_buf)
return 0;
if (is_emp_buf_change()) {
rx.new_emp_pkt = true;
memcpy(pre_emp_buf, emp_buf, rx.emp_buff.emp_pkt_cnt * 32);
rx.emp_buff.pre_emp_pkt_cnt = rx.emp_buff.emp_pkt_cnt;
} else {
rx.new_emp_pkt = false;
}
memset(pd_fifo_buf, 0, PFIFO_SIZE);
memset(&prx->emp_info, 0, sizeof(struct pd_infoframe_s));
pkt_num = rx.emp_buff.emp_pkt_cnt;
if (log_level & 0x4000)
rx_pr("pkt=%d\n", pkt_num);
if (log_level & PACKET_LOG)
rx_pr("emp pkt=%d\n", pkt_num);
#ifdef MULTI_VSIF_EXPORT_TO_EMP
rx.vs_info_details.vsi_state = 0x0;
rx_pkt_buffclear(PKT_TYPE_INFOFRAME_VSI);
#endif
while (pkt_num) {
pkt_num--;
/*read one pkt from fifo*/
@@ -2201,10 +2413,13 @@ int rx_pkt_handler(enum pkt_decode_type pkt_int_src)
28);
}
rxpktsts.fifo_pkt_num++;
if (log_level & PACKET_LOG)
rx_pr("PD[%d]=%x\n", rxpktsts.fifo_pkt_num, pd_fifo_buf[0]);
if (log_level & PACKET_LOG && rx.new_emp_pkt)
rx_pr("PD[0/%d]=0x%x, PD[1/%d]=0x%x\n",
pkt_num, pd_fifo_buf[0], pkt_num, pd_fifo_buf[1]);
pktdata = (union infoframe_u *)pd_fifo_buf;
rx_pkt_fifodecode(prx, pktdata, &rxpktsts);
if ((pd_fifo_buf[0] & 0xff) == PKT_TYPE_EMP)
rx_parse_dsf((u8 *)pd_fifo_buf);
if ((pd_fifo_buf[0] & 0xff) == PKT_TYPE_EMP && !find_emp_header) {
find_emp_header = true;
rx.emp_buff.ogi_id =
@@ -2237,70 +2452,116 @@ int rx_pkt_handler(enum pkt_decode_type pkt_int_src)
return 0;
}
#define VTEM_OGI_ID 1
#define VTEM_TAG_ID 1
void rx_get_vtem_info(void)
void rx_get_em_info(void)
{
u8 tmp;
u8 i, tmp;
int emp_type = -1;
u32 u_ieee;
struct emp_pkt_st *pkt;
pkt = (struct emp_pkt_st *)&rx_pkt.emp_info;
if (rx.chip_id < CHIP_ID_T7)
if (rx.chip_id < CHIP_ID_T7 || !rx.emp_pkt_rev) {
if (log_level == 0x121)
rx_pr("rx.emp_pkt_rev = %d\n", rx.emp_pkt_rev);
return;
if (log_level == 0x121) {
rx_pr("pkt->pkttype = %d", pkt->pkttype);
rx_pr("pkt->cnt.organization_id = %x", pkt->cnt.organization_id);
rx_pr("pkt->cnt.data_set_tag_lo = %x", pkt->cnt.data_set_tag_lo);
rx_pr("pkt->cnt.md[0] = %d", pkt->cnt.md[0]);
rx_pr("pkt->cnt.md[1] = %d", pkt->cnt.md[1]);
rx_pr("pkt->cnt.md[2] = %d", pkt->cnt.md[2]);
rx_pr("pkt->cnt.md[3] = %d", pkt->cnt.md[3]);
log_level = 1;
}
if (pkt->pkttype == PKT_TYPE_EMP &&
pkt->cnt.organization_id == VTEM_OGI_ID &&
pkt->cnt.data_set_tag_lo == VTEM_TAG_ID) {
tmp = pkt->cnt.md[0];
rx.vtem_info.vrr_en = tmp & 1;
rx.vtem_info.m_const = (tmp >> 1) & 1;
rx.vtem_info.qms_en = (tmp >> 2) & 1;
rx.vtem_info.fva_factor_m1 = (tmp >> 4) & 0x0f;
tmp = pkt->cnt.md[1];
rx.vtem_info.base_vfront = tmp;
tmp = pkt->cnt.md[2];
rx.vtem_info.rb = (tmp > 2) & 1;
rx.vtem_info.base_framerate = pkt->cnt.md[3];
rx.vtem_info.base_framerate |= (tmp & 3) << 8;
pkt->pkttype = 0;
} else {
rx.vtem_info.vrr_en = 0;
rx.vtem_info.m_const = 0;
rx.vtem_info.fva_factor_m1 = 0;
rx.vtem_info.base_vfront = 0;
rx.vtem_info.rb = 0;
rx.vtem_info.base_framerate = 0;
rx.sbtm_info.flag = false;
if (log_level == 0x121 && rx.emp_dsf_cnt)
rx_pr("emp_dsf_cnt:0x%x\n", rx.emp_dsf_cnt);
for (i = 0; i < rx.emp_dsf_cnt; i++) {
pkt = (struct emp_pkt_st *)rx.emp_dsf_info[i].pkt_addr;
u_ieee = pkt->cnt.md[0] +
(pkt->cnt.md[1] << 8) +
(pkt->cnt.md[2] << 16);
if (log_level == 0x121) {
rx_pr("---emp dsf params---\n");
rx_pr("pkttype = %d", pkt->pkttype);
rx_pr("ds_type=0x%x, sync=0x%x, vfr=0x%x, afr=0x%x\n",
pkt->cnt.ds_type, pkt->cnt.sync,
pkt->cnt.vfr, pkt->cnt.afr);
rx_pr("org_id = %x", pkt->cnt.organization_id);
rx_pr("data_tag = %x", pkt->cnt.data_set_tag_lo);
rx_pr("length = %x", pkt->cnt.data_set_length_lo);
if (!pkt->cnt.organization_id)
rx_pr("ieee = 0x%x", u_ieee);
rx_pr("md[0] = %d", pkt->cnt.md[0]);
rx_pr("md[1] = %d", pkt->cnt.md[1]);
rx_pr("md[2] = %d", pkt->cnt.md[2]);
rx_pr("md[3] = %d", pkt->cnt.md[3]);
}
if (pkt->cnt.organization_id == 0) {
if (pkt->cnt.data_set_tag_lo == 2 &&
u_ieee == IEEE_CUVAHDR) //cuva
emp_type = EMP_CUVA;
else if (u_ieee == IEEE_DV15) //dv
emp_type = EMP_DV;
} else if (pkt->cnt.organization_id == 1 &&
pkt->cnt.data_set_tag_lo == 1) {
emp_type = EMP_VTEM;//vtem
} else if (pkt->cnt.organization_id == 1 &&
pkt->cnt.data_set_tag_lo == 3 &&
pkt->cnt.ds_type == 1 &&
pkt->cnt.sync == 1 &&
pkt->cnt.vfr == 1 &&
pkt->cnt.afr == 0) {
emp_type = EMP_SBTM;//sbtm
}
switch (emp_type) {
case EMP_VTEM:
tmp = pkt->cnt.md[0];
rx.vtem_info.vrr_en = tmp & 1;
rx.vtem_info.m_const = (tmp >> 1) & 1;
rx.vtem_info.qms_en = (tmp >> 2) & 1;
rx.vtem_info.fva_factor_m1 = (tmp >> 4) & 0x0f;
tmp = pkt->cnt.md[1];
rx.vtem_info.base_vfront = tmp;
tmp = pkt->cnt.md[2];
rx.vtem_info.rb = (tmp > 2) & 1;
rx.vtem_info.base_framerate = pkt->cnt.md[3];
rx.vtem_info.base_framerate |= (tmp & 3) << 8;
pkt->pkttype = 0;
break;
case EMP_SBTM:
tmp = pkt->cnt.md[0];
rx.sbtm_info.sbtm_ver = tmp & 0x0f;
tmp = pkt->cnt.md[1];
rx.sbtm_info.sbtm_mode = tmp & 3;
rx.sbtm_info.sbtm_type = (tmp >> 2) & 3;
rx.sbtm_info.grdm_min = (tmp >> 4) & 3;
rx.sbtm_info.grdm_lum = (tmp >> 6) & 3;
tmp = pkt->cnt.md[2];
rx.sbtm_info.frm_pb_limit_int = tmp & 0x1f;
rx.sbtm_info.frm_pb_limit_int <<= 8;
tmp = pkt->cnt.md[3];
rx.sbtm_info.frm_pb_limit_int |= tmp;
pkt->pkttype = 0;
rx.sbtm_info.flag = true;
break;
case EMP_DV:
rx.emp_dv_info.flag = true;
rx.emp_dv_info.dv_addr = (u8 *)pkt;
rx.emp_dv_info.dv_size = rx.emp_dsf_info[i].pkt_cnt;
break;
case EMP_CUVA:
rx.emp_cuva_info.flag = true;
rx.emp_cuva_info.emds_addr = (u8 *)pkt;
rx.emp_cuva_info.cuva_emds_size =
rx.emp_dsf_info[i].pkt_cnt;
break;
default:
memset(&rx.vtem_info, 0, sizeof(struct vtem_info_s));
memset(&rx.sbtm_info, 0, sizeof(struct sbtm_info_s));
break;
};
}
//if (rx.vrr_en) {
//tmp = hdmirx_rd_cor(RX_VT_EMP_DBYTE0_DP0B_IVCRX);
//rx.vtem_info.vrr_en = tmp & 1;
//rx.vtem_info.m_const = (tmp >> 1) & 1;
//rx.vtem_info.qms_en = (tmp >> 2) & 1;
//rx.vtem_info.fva_factor_m1 = (tmp >> 4) & 0x0f;
//tmp = hdmirx_rd_cor(RX_VT_EMP_DBYTE1_DP0B_IVCRX);
//rx.vtem_info.base_vfront = tmp;
//tmp = hdmirx_rd_cor(RX_VT_EMP_DBYTE2_DP0B_IVCRX);
//rx.vtem_info.rb = (tmp > 2) & 1;
//rx.vtem_info.base_framerate = hdmirx_rd_cor(RX_VT_EMP_DBYTE3_DP0B_IVCRX);
//rx.vtem_info.base_framerate |= (tmp & 3) << 8;
//} else {
//rx.vtem_info.vrr_en = 0;
//rx.vtem_info.m_const = 0;
//rx.vtem_info.fva_factor_m1 = 0;
///rx.vtem_info.base_vfront = 0;
///rx.vtem_info.rb = 0;
///rx.vtem_info.base_framerate = 0;
//}
rx.emp_pkt_rev = false;
rx.emp_dsf_cnt = 0;
for (i = 0; i < EMP_DSF_CNT_MAX; i++)
memset(&rx.emp_dsf_info[i], 0, sizeof(struct pd_infoframe_s));
if (log_level == 0x121)
log_level = LOG_EN;
}
void rx_get_aif_info(void)
drivers/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.h
+41 -8
View File
@@ -14,19 +14,23 @@
#define K_FLAG_TAB_END 0xa0a05f5f
#define VSIF_PKT_READ_FROM_PD_FIFO
//#define VSIF_PKT_READ_FROM_PD_FIFO
#define IEEE_VSI14 0x000c03
#define IEEE_DV15 0x00d046
#define IEEE_VSI21 0xc45dd8
#define IEEE_HDR10PLUS 0x90848b
#define IEEE_CUVAHDR 0x047503
#define IEEE_DV_PLUS_ALLM 0x1
#define IEEE_HDR10P_PLUS_ALLM 0x2
#define IEEE_FREESYNC 0x00001a
#define VSIF_TYPE_DV15 1
#define VSIF_TYPE_HDR10P 2
#define VSIF_TYPE_HDMI21 4
#define VSIF_TYPE_HDMI14 8
#define VSIF_TYPE_CUVA 16
#define EMP_TYPE_VSIF 1
#define EMP_TYPE_VTEM 2
@@ -37,12 +41,22 @@
#define DV_EMP 2
enum vsi_state_e {
E_VSI_NULL,
E_VSI_4K3D,
E_VSI_VSI21,
E_VSI_HDR10PLUS,
E_VSI_DV10,
E_VSI_DV15
E_VSI_NULL = 0,
E_VSI_4K3D = 0x01,
E_VSI_VSI21 = 0x02,
E_VSI_HDR10PLUS = 0x04,
E_VSI_DV10 = 0x08,
E_VSI_DV15 = 0x10,
E_VSI_CUVAHDR = 0x20,
};
enum vsi_type {
DV15,
CUVAHDR,
HDR10PLUS,
VSI21,
VSI14,
VSI_TYPE_MAX
};
enum pkt_length_e {
@@ -713,6 +727,17 @@ struct vsi_infoframe_st {
u8 data[22];
/*todo*/
} __packed vsi_st_21;
/* CUVA HDR ieee 0x047503 */
struct vsi_cuva_hdr {
/*pb4*/
u8 sys_start_code:8;
/*pb5*/
u8 rsvd1:2;
u8 transfer_char:1;
u8 monitor_mode_enable:1;
u8 version_code:4;
} __packed vsi_cuva_hdr;
} __packed sbpkt;
} __packed;
@@ -1031,9 +1056,17 @@ struct pd_infoframe_s {
u32 PB6;
};
enum emp_pkt_type_e {
EMP_VTEM,
EMP_SBTM,
EMP_DV,
EMP_CUVA
};
struct packet_info_s {
/* packet type 0x81 vendor-specific */
struct pd_infoframe_s vs_info;
struct pd_infoframe_s multi_vs_info[VSI_TYPE_MAX];
/* packet type 0x82 AVI */
struct pd_infoframe_s avi_info;
/* packet type 0x83 source product description */
@@ -1151,7 +1184,7 @@ u32 rx_pkt_chk_busy_drm(void);
void rx_get_pd_fifo_param(enum pkt_type_e pkt_type,
struct pd_infoframe_s *pkt_info);
void rx_get_avi_info(struct avi_infoframe_st *st_pkt);
void rx_get_vtem_info(void);
void rx_get_em_info(void);
void rx_get_aif_info(void);
void dump_pktinfo_status(void);
bool rx_is_specific_20_dev(void);
drivers/media/vin/tvin/hdmirx/hdmi_rx_repeater.h
+8 -1
View File
@@ -76,7 +76,14 @@ extern u8 ksvlist[10];
int rx_hdmi_tx_notify_handler(struct notifier_block *nb,
unsigned long value, void *p);
#ifdef CONFIG_AMLOGIC_HDMITX
u8 hdmitx_reauth_request(u8 hdcp_version);
#else
u8 __weak hdmitx_reauth_request(u8 hdcp_version)
{
return 0;
}
#endif
void rx_set_repeater_support(bool enable);
bool get_rx_active_sts(void);
//int rx_set_receiver_edid(const char *data, int len);
drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
+16 -16
View File
@@ -470,7 +470,7 @@ int cec_set_dev_info(u8 dev_idx)
if (dev_idx == 1)
hdcp_enc_mode = 1;
if (dev_idx == 2 && cec_dev_en)
dev_is_appletv_v2 = 1;
dev_is_apple_tv_v2 = 1;
rx_pr("cec special dev = %x", dev_idx);
return 0;
}
@@ -1102,6 +1102,7 @@ irqreturn_t irq_handler(int irq, void *params)
rx.state = FSM_WAIT_CLK_STABLE;
irq_err_cnt = 0;
}
if (params == 0) {
rx_pr("%s: %s\n", __func__,
"RX IRQ invalid parameter");
@@ -1163,10 +1164,12 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
#endif
if (rx.state == FSM_SIG_READY) {
rx.vsync_cnt++;
#ifndef MULTI_VSIF_EXPORT_TO_EMP
if (rx_vsif_type) {
rx_pkt_handler(PKT_BUFF_SET_VSI);
rx_vsif_type = 0;
}
#endif
if (rx_spd_type) {
rx_pkt_handler(PKT_BUFF_SET_SPD);
rx_spd_type = 0;
@@ -1177,8 +1180,8 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
} else {
rx.vrr_en = false;
}
if (rx.chip_id >= CHIP_ID_T7)
rx_check_ecc_error();
//if (rx.chip_id >= CHIP_ID_T7)
//rx_check_ecc_error();
rx_update_sig_info();
}
if (log_level & 0x400)
@@ -1375,27 +1378,23 @@ static bool fmt_vic_abnormal(void)
*/
if (rx.pre.sw_vic == HDMI_UNKNOWN ||
rx.pre.sw_vic == HDMI_UNSUPPORT) {
if (log_level & VIDEO_LOG)
rx_pr("unsupport fmt!\n");
rx_pr("unsupport fmt!\n");
return true;
} else if (rx.pre.sw_vic >= HDMI_VESA_OFFSET &&
rx.pre.sw_vic < HDMI_UNSUPPORT &&
rx.pre.repeat != 0) {
/* no pixel repetition for VESA mode */
if (log_level & VIDEO_LOG)
rx_pr("repetition abnormal for vesa\n");
return true;
} else if ((rx.pre.sw_vic == HDMI_1080p_ALTERNATIVE) &&
(rx.pre.sw_dvi ||
rx.pre.colorspace == E_COLOR_YUV420 ||
rx.vs_info_details._3d_structure == 0)) {
if (log_level & VIDEO_LOG)
rx_pr("avi abnormal for 3dmode\n");
rx_pr("avi abnormal for 3dmode\n");
return true;
} else if ((rx.cur.hdcp22_state & 1) &&
rx.cur.hdcp14_state == 3) {
if (log_level & VIDEO_LOG)
rx_pr("hdcp sts err\n");
rx_pr("hdcp sts err\n");
return false;
}
return false;
@@ -2105,7 +2104,7 @@ void rx_dwc_reset(void)
rx_sw_reset(rst_lvl);
//rx_irq_en(true);
/* for hdcp1.4 interact very early cases, don't do
* esm reset to avoid interaction be interferenced.
* esm reset to avoid interaction be interference.
*/
rx_esm_reset(3);
}
@@ -2200,7 +2199,7 @@ bool is_unnormal_format(u8 wait_cnt)
*/
if (rx.hdcp.hdcp_version == HDCP_VER_NONE) {
ret = true;
if (dev_is_appletv_v2) {
if (dev_is_apple_tv_v2) {
if (wait_cnt == hdcp_none_wait_max * 30)
ret = false;
} else if (rx.hdcp.hdcp_pre_ver != HDCP_VER_14) {
@@ -3456,7 +3455,7 @@ void rx_main_state_machine(void)
/*sizeof(struct aud_info_s));*/
/*rx_set_eq_run_state(E_EQ_PASS);*/
hdmirx_config_video();
rx_get_audinfo(&rx.aud_info);
rx_get_aud_info(&rx.aud_info);
hdmirx_config_audio();
rx_aud_pll_ctl(1);
rx_afifo_store_all_subpkt(false);
@@ -3617,7 +3616,7 @@ void rx_main_state_machine(void)
hdcp_sts_update();
pre_auds_ch_alloc = rx.aud_info.auds_ch_alloc;
pre_auds_hbr = rx.aud_info.aud_hbr_rcv;
rx_get_audinfo(&rx.aud_info);
rx_get_aud_info(&rx.aud_info);
if (check_real_sr_change())
rx_audio_pll_sw_update();
@@ -3885,6 +3884,7 @@ static void dump_video_status(void)
rx_pr("cnt_type = %d\n", rx.cur.cn_type);
rx_pr("dolby_vision = %d\n", rx.vs_info_details.dolby_vision_flag);
rx_pr("dv ll = %d\n", rx.vs_info_details.low_latency);
rx_pr("cuva hdr = %d\n", rx.vs_info_details.cuva_hdr);
//rx_pr("VTEM = %d\n", rx.vrr_en);
rx_pr("DRM = %d\n", rx_pkt_chk_attach_drm());
rx_pr("freesync = %d\n-bit0 supported,bit1:enabled.bit2:active", rx.free_sync_sts);
@@ -3900,7 +3900,7 @@ static void dump_audio_status(void)
static struct aud_info_s a;
u32 val0, val1;
rx_get_audinfo(&a);
rx_get_aud_info(&a);
rx_pr("[AudioInfo]\n");
rx_pr(" CT=%u CC=%u", a.coding_type,
a.channel_count);
@@ -4313,7 +4313,7 @@ void hdmirx_timer_handler(struct timer_list *t)
rx_check_repeat();
if (!(rpt_only_mode && !rx.hdcp.repeat)) {
if (!sm_pause) {
rx_clkrate_monitor();
rx_clk_rate_monitor();
rx_afifo_monitor();
rx_ddc_active_monitor();
rx_hdcp_monitor();
drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h
-8
View File
@@ -162,12 +162,4 @@ int __weak get_video_mute(void)
{
return 0;
}
#ifdef CONFIG_AMLOGIC_HDMITX
u8 hdmitx_reauth_request(u8 hdcp_version);
#endif
u8 __weak hdmitx_reauth_request(u8 hdcp_version)
{
return 0;
}
#endif
drivers/media/vin/tvin/tvin_global.h
+81 -10
View File
@@ -462,16 +462,63 @@ struct tvin_vtem_data_s {
u8 base_v_front;
u8 rb;
u16 base_framerate;
//real structure
//u8 vrr_en:1;
//u8 m_const:1;
//u8 qms:2;
//u8 fva_factor_m1:4;
//u8 base_vfront;
//u8 base_fr_high:2;
//u8 rb:1;
//u8 rsvd1:5;
//u8 base_fr_low;
};
struct tvin_cuva_emds_data_s {
/* Sequence_Index:0 */
u8 pkt_type_0;
u8 hb1_0;
u8 sequence_index_0;
u8 pb0;
u16 organization_id;
u16 data_tag;
u16 data_length;
u32 ieee:24;
u32 system_start_code:8;
u16 min_maxrgb_pq;
u16 avg_maxrgb_pq;
u16 var_maxrgb_pq;
u16 max_maxrgb_pq;
u16 targeted_max_lum_pq;
u16 base_param_m_p;
u8 base_param_m_m;
u16 base_param_m_a;
u16 base_param_m_b;
/* Sequence_Index:1 */
u8 pkt_type_1;
u8 hb1_1;
u8 sequence_index_1;
u8 base_param_m_n;
u8 base_param_k;
u8 base_param_delta_enable_mode;
u8 base_param_enable_delta;
struct {
u8 th_enable_mode;
u8 th_enable_mb;
u16 th_enable;
u16 th_enable_delta[2];
u8 enable_strength;
} _3spline_data[2];
u8 color_saturation_num;
u8 color_saturation_gain0[5];
/* Sequence_Index:2 */
u8 pkt_type_2;
u8 hb1_2;
u8 sequence_index_2;
u8 color_saturation_gain1[3];
u8 graphic_src_display_value;
u8 rvd;
u16 max_display_mastering_lum;
u8 rvd1[21];
};
struct tvin_sbtm_data_s {
u8 sbtm_ver;
u8 sbtm_mode;
u8 sbtm_type;
u8 grdm_min;
u8 grdm_lum;
u16 frm_pb_limit_int;
};
struct tvin_spd_data_s {
@@ -490,6 +537,27 @@ struct tvin_hdr10plus_info_s {
struct tvin_hdr10p_data_s hdr10p_data;
};
struct tvin_cuva_data_s {
u8 vsif_type; //hb0
u8 visf_version; //hb1
u8 payload_length; //hb2
u8 check_sum; //pb0
u32 ieee:24; //pb1-3
u8 sys_start_code; //pb4
/* pb5 */
u8 rsvd:2;
u8 transfer_char:1;
u8 monitor_mode_enable:1;
u8 version_code:4;
/* pb6-pb27 */
u8 reserved[22];
};
struct tvin_cuva_vsif_s {
bool cuva_on;
struct tvin_cuva_data_s cuva_data;
};
enum tvin_cn_type_e {
GRAPHICS,
PHOTO,
@@ -527,6 +595,7 @@ struct tvin_sig_property_s {
enum tvin_color_fmt_range_e color_fmt_range;
struct tvin_hdr_info_s hdr_info;
struct tvin_dv_vsif_s dv_vsif;/*dolby vsi info*/
struct tvin_cuva_vsif_s cuva_info; /* cuva hdr info */
struct tvin_dv_vsif_raw_s dv_vsif_raw;
u8 dolby_vision;/*is signal dolby version 1:vsif 2:emp */
bool low_latency;/*is low latency dolby mode*/
@@ -536,6 +605,8 @@ struct tvin_sig_property_s {
struct tvin_hdr10plus_info_s hdr10p_info;
struct tvin_emp_data_s emp_data;
struct tvin_vtem_data_s vtem_data;
struct tvin_sbtm_data_s sbtm_data;
struct tvin_cuva_emds_data_s cuva_emds_data;
struct tvin_spd_data_s spd_data;
unsigned int cnt;
unsigned int hw_vic;