mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
clk: s6: Fix known issue [1/1]
PD#SWPL-179629 Problem: 1 Optimize driver file formats using automated tools. 2 vpu_clk adds a flag feature to prevent glitch when operating the clock. 3 The naming of hifi_pll is inconsistent with the clkid style. 4 The latest documentation provided by vlsi has changed the sys_clk definition for USB and PCIe. Solution: 1 Optimized 2 vpu_clk added flag CLK_OPS_PARENT_ENABLE. 3 The clkid of hifi_pll is named CLKID_HIFI_PLL. 4 USB and PCIe sys_clk have been updated. Verify: s6_bl201 Change-Id: I4560f7bc6d42583d4e62d184c182bfe199cb6955 Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
This commit is contained in:
Chuan Liu
committed by
gerrit autosubmit
gerrit autosubmit
parent
f9e4d31ce9
commit
40e030d862
@@ -693,7 +693,7 @@
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compatible = "amlogic,g12a-mdio-mux";
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reg = <0x0 0x360000 0x0 0xa4>;
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clocks = <&clkc CLKID_SYS_ETHPHY>,
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clocks = <&clkc CLKID_SYS_ETH_PHY>,
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<&xtal>,
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<&clkc CLKID_FCLK50M>;
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clock-names = "pclk", "clkin0", "clkin1";
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@@ -765,7 +765,7 @@
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reset-level = <0x40>;
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usb-phy-trim-reg = <0xfe010330>;
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phy-id = <0>;
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clocks = <&clkc CLKID_SYS_USB>;
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clocks = <&clkc CLKID_SYS_USB2DRD>;
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clock-names = "crg_general";
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pm-controller;
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};
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@@ -785,7 +785,7 @@
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reset-level = <0x40>;
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usb-phy-trim-reg = <0xfe010330>;
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phy-id = <1>;
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clocks = <&clkc CLKID_SYS_USB>;
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clocks = <&clkc CLKID_SYS_USB3DRD>;
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clock-names = "crg_general";
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pm-controller;
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};
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@@ -807,7 +807,7 @@
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usb3-controller-reset-bit = /bits/ 8 <5>;
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reset-level-shift = <0x40>;
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phy-id = /bits/ 8 <1>;
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clocks = <&clkc CLKID_SYS_USB>,
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clocks = <&clkc CLKID_SYS_USB3DRD>,
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<&clkc CLKID_USB_250M>;
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clock-names = "u3p_clk_0",
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"u3p_clk_1";
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@@ -832,7 +832,7 @@
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reg = <0x0 0xfe340000 0x0 0x8000>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>;
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usb-phy = <&usb_phy20>, <&usb_phy30>;
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clocks = <&clkc CLKID_SYS_USB>;
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clocks = <&clkc CLKID_SYS_USB2DRD>;
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clock-names = "crg_general";
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dma-64bit-support = <1>;
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in-nak-rty = <0x5>;
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@@ -847,7 +847,7 @@
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port-speed = <3>; /* 0~3: unknown, low, full, high */
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phy-reg = <0xfe348000>; /* phy2 base*/
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phy-reg-size = <0x10>;
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clocks = <&clkc CLKID_SYS_USB>;
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clocks = <&clkc CLKID_SYS_USB2DRD>;
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clock-names = "usb_general";
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phy-id = <0>;
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version = <1>; /* 1: forbid vbus detect */
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@@ -860,7 +860,7 @@
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reg = <0x0 0xfe350000 0x0 0x8000>;
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interrupts = <0 130 IRQ_TYPE_EDGE_RISING>;
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usb-phy = <&usb_phy21>, <&usb_phy31>;
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clocks = <&clkc CLKID_SYS_USB>;
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clocks = <&clkc CLKID_SYS_USB3DRD>;
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clock-names = "crg_general";
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dma-64bit-support = <1>;
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in-nak-rty = <0x5>;
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@@ -923,7 +923,7 @@
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* pinctrl-0 = <&pcieck_pins>;
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*/
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clocks = <&clkc CLKID_SYS_PCIE>,
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clocks = <&clkc CLKID_SYS_PCIE_MAC>,
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<&clkc CLKID_SYS_PCIE_PHY>,
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<&clkc CLKID_PCIE_TL>;
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clock-names = "pcie",
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@@ -1064,7 +1064,7 @@
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<0x0 0xfe364000 0x0 0x8>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_SYS_ETHPHY>,
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clocks = <&clkc CLKID_SYS_ETH_MAC>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_FCLK50M>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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@@ -162,7 +162,7 @@
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dai-tdm-lane-slot-mask-out = <1 0>;
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dai-tdm-clk-sel = <0>;
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clocks = <&clkaudio CLKID_AUDIO_MCLK_A
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL>;
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clock-names = "mclk", "clk_srcpll", "clk_src_cd";
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suspend-clk-off = <1>;
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@@ -179,7 +179,7 @@
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dai-tdm-lane-slot-mask-out = <1 1 1 1>;
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dai-tdm-clk-sel = <1>;
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clocks = <&clkaudio CLKID_AUDIO_MCLK_B
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL>;
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clock-names = "mclk", "clk_srcpll", "clk_src_cd";
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suspend-clk-off = <1>;
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@@ -198,7 +198,7 @@
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dai-tdm-clk-sel = <2>;
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clocks = <&clkaudio CLKID_AUDIO_MCLK_C
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL>;
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clock-names = "mclk", "clk_srcpll", "clk_src_cd";
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@@ -223,7 +223,7 @@
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clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
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&clkc CLKID_FCLK_DIV3
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_PDMIN0
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&clkaudio CLKID_AUDIO_PDMIN1>;
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clock-names = "gate",
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@@ -244,7 +244,7 @@
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compatible = "amlogic, tm2-revb-snd-spdif-a";
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#sound-dai-cells = <0>;
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clocks = <&clkc CLKID_HIFI0_PLL
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clocks = <&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL
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&clkc CLKID_FCLK_DIV4
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&clkaudio CLKID_AUDIO_GATE_SPDIFIN
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@@ -277,7 +277,7 @@
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compatible = "amlogic, tm2-revb-snd-spdif-b";
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#sound-dai-cells = <0>;
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clocks = <&clkc CLKID_HIFI0_PLL /*CLKID_HIFI0_PLL*/
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clocks = <&clkc CLKID_HIFI_PLL /*CLKID_HIFI_PLL*/
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&clkc CLKID_HIFI1_PLL
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&clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B
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&clkaudio CLKID_AUDIO_SPDIFOUT_B>;
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@@ -326,7 +326,7 @@
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asrca: resample@0 {
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compatible = "amlogic, t5-resample-a";
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clocks = <&clkc CLKID_HIFI0_PLL
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clocks = <&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_MCLK_B
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&clkaudio CLKID_AUDIO_RESAMPLE_A>;
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clock-names = "resample_pll", "resample_src", "resample_clk";
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@@ -353,7 +353,7 @@
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asrcb: resample@1 {
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compatible = "amlogic, t5-resample-b";
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clocks = <&clkc CLKID_HIFI0_PLL
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clocks = <&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_MCLK_F
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&clkaudio CLKID_AUDIO_RESAMPLE_B>;
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clock-names = "resample_pll", "resample_src", "resample_clk";
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@@ -406,10 +406,10 @@
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clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
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&clkc CLKID_FCLK_DIV3
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_PDMIN0
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&clkaudio CLKID_AUDIO_PDMIN1
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_MCLK_A>;
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clock-names = "pdm_gate",
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"pdm_sysclk_srcpll",
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@@ -462,10 +462,10 @@
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clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
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&clkc CLKID_FCLK_DIV3
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_PDMIN0
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&clkaudio CLKID_AUDIO_PDMIN1
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkaudio CLKID_AUDIO_MCLK_A>;
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clock-names = "pdm_gate",
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"pdm_sysclk_srcpll",
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@@ -1601,7 +1601,7 @@
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&tdmc {
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clocks = <&clkaudio CLKID_AUDIO_MCLK_C
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL
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&clkaudio CLKID_AUDIO_MCLK_PAD1>;
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clock-names = "mclk", "clk_srcpll", "clk_src_cd", "mclk_pad";
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@@ -1536,7 +1536,7 @@
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&tdmc {
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clocks = <&clkaudio CLKID_AUDIO_MCLK_C
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL
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&clkaudio CLKID_AUDIO_MCLK_PAD1>;
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clock-names = "mclk", "clk_srcpll", "clk_src_cd", "mclk_pad";
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@@ -1561,7 +1561,7 @@
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&tdmc {
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clocks = <&clkaudio CLKID_AUDIO_MCLK_C
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&clkc CLKID_HIFI0_PLL
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&clkc CLKID_HIFI_PLL
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&clkc CLKID_HIFI1_PLL
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&clkaudio CLKID_AUDIO_MCLK_PAD1>;
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clock-names = "mclk", "clk_srcpll", "clk_src_cd", "mclk_pad";
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+421
-460
File diff suppressed because it is too large
Load Diff
+21
-135
@@ -6,64 +6,55 @@
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#ifndef __S6_H
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#define __S6_H
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/*
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* Clock controller register offsets
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* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
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*/
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#define CLKCTRL_OSCIN_CTRL (0x0001 << 2)
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#define ANACTRL_FIXPLL_CTRL1 (0x0011 << 2)
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#define ANACTRL_GP0PLL_CTRL0 (0x0020 << 2)
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#define ANACTRL_GP0PLL_CTRL1 (0x0021 << 2)
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#define ANACTRL_GP0PLL_CTRL2 (0x0022 << 2)
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#define ANACTRL_GP0PLL_CTRL3 (0x0023 << 2)
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#define ANACTRL_GP0PLL_CTRL4 (0x0024 << 2)
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#define ANACTRL_HIFI0PLL_CTRL0 (0x0040 << 2)
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#define ANACTRL_HIFI0PLL_CTRL1 (0x0041 << 2)
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#define ANACTRL_HIFI0PLL_CTRL2 (0x0042 << 2)
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#define ANACTRL_HIFI0PLL_CTRL3 (0x0043 << 2)
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#define ANACTRL_HIFI0PLL_CTRL4 (0x0044 << 2)
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#define ANACTRL_HIFI1PLL_CTRL0 (0x0045 << 2)
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#define ANACTRL_HIFI1PLL_CTRL1 (0x0046 << 2)
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#define ANACTRL_HIFI1PLL_CTRL2 (0x0047 << 2)
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#define ANACTRL_HIFI1PLL_CTRL3 (0x0048 << 2)
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#define ANACTRL_HIFI1PLL_CTRL4 (0x0049 << 2)
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#define ANACTRL_CSIPLL_CTRL0 (0x0098 << 2)
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#define ANACTRL_CSIPLL_CTRL1 (0x0099 << 2)
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#define ANACTRL_CSIPLL_CTRL2 (0x009a << 2)
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#define ANACTRL_CSIPLL_CTRL3 (0x009b << 2)
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#define CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2)
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#define CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2)
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#define CLKCTRL_RTC_CTRL (0x0004 << 2)
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#define CLKCTRL_CHECK_CLK_RESULT (0x0005 << 2)
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#define CLKCTRL_MBIST_ATSPEED_CTRL (0x0006 << 2)
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#define CLKCTRL_LOCK_BIT_REG0 (0x0008 << 2)
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#define CLKCTRL_LOCK_BIT_REG1 (0x0009 << 2)
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#define CLKCTRL_LOCK_BIT_REG2 (0x000a << 2)
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#define CLKCTRL_LOCK_BIT_REG3 (0x000b << 2)
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#define CLKCTRL_PROT_BIT_REG0 (0x000c << 2)
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#define CLKCTRL_PROT_BIT_REG1 (0x000d << 2)
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#define CLKCTRL_PROT_BIT_REG2 (0x000e << 2)
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#define CLKCTRL_PROT_BIT_REG3 (0x000f << 2)
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#define CLKCTRL_SYS_CLK_CTRL0 (0x0010 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2)
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#define CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2)
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#define CLKCTRL_SYS_CLK_EN1_REG0 (0x0015 << 2)
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#define CLKCTRL_SYS_CLK_EN1_REG1 (0x0016 << 2)
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#define CLKCTRL_SYS_CLK_EN1_REG2 (0x0017 << 2)
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#define CLKCTRL_SYS_CLK_EN1_REG3 (0x0018 << 2)
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#define CLKCTRL_SYS_CLK_VPU_EN0 (0x0019 << 2)
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#define CLKCTRL_SYS_CLK_VPU_EN1 (0x001a << 2)
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#define CLKCTRL_AXI_CLK_CTRL0 (0x001b << 2)
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#define CLKCTRL_TST_CTRL0 (0x0020 << 2)
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#define CLKCTRL_TST_CTRL1 (0x0021 << 2)
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#define CLKCTRL_CECB_CTRL0 (0x0024 << 2)
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#define CLKCTRL_CECB_CTRL1 (0x0025 << 2)
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#define CLKCTRL_SC_CLK_CTRL (0x0026 << 2)
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#define CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2)
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#define CLKCTRL_RAMA_CLK_CTRL0 (0x0029 << 2)
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#define CLKCTRL_CLK12_24_CTRL (0x002a << 2)
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#define CLKCTRL_AXI_CLK_EN0 (0x002b << 2)
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#define CLKCTRL_AXI_CLK_EN1 (0x002c << 2)
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#define CLKCTRL_VID_CLK_CTRL (0x0030 << 2)
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#define CLKCTRL_VID_CLK_CTRL2 (0x0031 << 2)
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#define CLKCTRL_VID_CLK_DIV (0x0032 << 2)
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#define CLKCTRL_VIID_CLK_DIV (0x0033 << 2)
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#define CLKCTRL_VIID_CLK_CTRL (0x0034 << 2)
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#define CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2)
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#define CLKCTRL_VID_PLL_CLK_DIV (0x0039 << 2)
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#define CLKCTRL_VPU_CLK_CTRL (0x003a << 2)
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#define CLKCTRL_VPU_CLKB_CTRL (0x003b << 2)
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#define CLKCTRL_VPU_CLKC_CTRL (0x003c << 2)
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#define CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2)
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#define CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2)
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#define CLKCTRL_VAPBCLK_CTRL (0x003f << 2)
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#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL (0x0041 << 2)
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#define CLKCTRL_CDAC_CLK_CTRL (0x0042 << 2)
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#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0043 << 2)
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#define CLKCTRL_CSI2_ADAPT_CLK_CTRL (0x0044 << 2)
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#define CLKCTRL_DSI_PLL_CLK_DIV (0x0045 << 2)
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#define CLKCTRL_HTX_CLK_CTRL0 (0x0047 << 2)
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#define CLKCTRL_HTX_CLK_CTRL1 (0x0048 << 2)
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#define CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2)
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@@ -91,110 +82,5 @@
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#define CLKCTRL_PCIE_CLK_CTRL (0x0069 << 2)
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#define CLKCTRL_CMPR_CLK_CTRL (0x006a << 2)
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#define CLKCTRL_DEWARPA_CLK_CTRL (0x006b << 2)
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#define CLKCTRL_TIMESTAMP_CTRL (0x0100 << 2)
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#define CLKCTRL_TIMESTAMP_CTRL1 (0x0101 << 2)
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#define CLKCTRL_TIMESTAMP_CTRL2 (0x0103 << 2)
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#define CLKCTRL_TIMESTAMP_RD0 (0x0104 << 2)
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#define CLKCTRL_TIMESTAMP_RD1 (0x0105 << 2)
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#define CLKCTRL_TIMEBASE_CTRL0 (0x0106 << 2)
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#define CLKCTRL_TIMEBASE_CTRL1 (0x0107 << 2)
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#define CLKCTRL_EFUSE_CPU_CFG01 (0x0120 << 2)
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#define CLKCTRL_EFUSE_CPU_CFG2 (0x0121 << 2)
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#define CLKCTRL_EFUSE_ENCP_CFG0 (0x0122 << 2)
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#define CLKCTRL_EFUSE_MALI_CFG01 (0x0123 << 2)
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#define CLKCTRL_EFUSE_HEVCB_CFG01 (0x0124 << 2)
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#define CLKCTRL_EFUSE_HEVCB_CFG2 (0x0125 << 2)
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#define CLKCTRL_EFUSE_LOCK (0x0126 << 2)
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#define CLKCTRL_EFUSE_MALI_STACK_CFG01 (0x0127 << 2)
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/* ANA_CTRL - Registers
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*REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
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*/
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#define ANACTRL_SYS0PLL_CTRL0 (0x0000 << 2)
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#define ANACTRL_SYS0PLL_CTRL1 (0x0001 << 2)
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#define ANACTRL_SYS0PLL_CTRL2 (0x0002 << 2)
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#define ANACTRL_SYS0PLL_CTRL3 (0x0003 << 2)
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#define ANACTRL_SYS1PLL_CTRL0 (0x0004 << 2)
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#define ANACTRL_SYS1PLL_CTRL1 (0x0005 << 2)
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#define ANACTRL_SYS1PLL_CTRL2 (0x0006 << 2)
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#define ANACTRL_SYS1PLL_CTRL3 (0x0007 << 2)
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#define ANACTRL_SYS0PLL_STS (0x0008 << 2)
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#define ANACTRL_SYS1PLL_STS (0x0009 << 2)
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#define ANACTRL_FIXPLL_CTRL0 (0x0010 << 2)
|
||||
#define ANACTRL_FIXPLL_CTRL1 (0x0011 << 2)
|
||||
#define ANACTRL_FIXPLL_CTRL2 (0x0012 << 2)
|
||||
#define ANACTRL_FIXPLL_CTRL3 (0x0013 << 2)
|
||||
#define ANACTRL_FIXPLL_CTRL4 (0x0014 << 2)
|
||||
#define ANACTRL_FIXPLL_STS (0x0017 << 2)
|
||||
#define ANACTRL_GP0PLL_CTRL0 (0x0020 << 2)
|
||||
#define ANACTRL_GP0PLL_CTRL1 (0x0021 << 2)
|
||||
#define ANACTRL_GP0PLL_CTRL2 (0x0022 << 2)
|
||||
#define ANACTRL_GP0PLL_CTRL3 (0x0023 << 2)
|
||||
#define ANACTRL_GP0PLL_CTRL4 (0x0024 << 2)
|
||||
#define ANACTRL_GP0PLL_STS (0x0027 << 2)
|
||||
#define ANACTRL_GP1PLL_CTRL0 (0x0030 << 2)
|
||||
#define ANACTRL_GP1PLL_CTRL1 (0x0031 << 2)
|
||||
#define ANACTRL_GP1PLL_CTRL2 (0x0032 << 2)
|
||||
#define ANACTRL_GP1PLL_CTRL3 (0x0033 << 2)
|
||||
#define ANACTRL_GP1PLL_STS (0x0037 << 2)
|
||||
#define ANACTRL_GP2PLL_CTRL0 (0x0050 << 2)
|
||||
#define ANACTRL_GP2PLL_CTRL1 (0x0051 << 2)
|
||||
#define ANACTRL_GP2PLL_CTRL2 (0x0052 << 2)
|
||||
#define ANACTRL_GP2PLL_CTRL3 (0x0053 << 2)
|
||||
#define ANACTRL_GP2PLL_STS (0x0057 << 2)
|
||||
#define ANACTRL_HIFI0PLL_CTRL0 (0x0040 << 2)
|
||||
#define ANACTRL_HIFI0PLL_CTRL1 (0x0041 << 2)
|
||||
#define ANACTRL_HIFI0PLL_CTRL2 (0x0042 << 2)
|
||||
#define ANACTRL_HIFI0PLL_CTRL3 (0x0043 << 2)
|
||||
#define ANACTRL_HIFI0PLL_CTRL4 (0x0044 << 2)
|
||||
#define ANACTRL_HIFI1PLL_CTRL0 (0x0045 << 2)
|
||||
#define ANACTRL_HIFI1PLL_CTRL1 (0x0046 << 2)
|
||||
#define ANACTRL_HIFI1PLL_CTRL2 (0x0047 << 2)
|
||||
#define ANACTRL_HIFI1PLL_CTRL3 (0x0048 << 2)
|
||||
#define ANACTRL_HIFI1PLL_CTRL4 (0x0049 << 2)
|
||||
#define ANACTRL_HIFI0PLL_STS (0x004a << 2)
|
||||
#define ANACTRL_HIFI1PLL_STS (0x004b << 2)
|
||||
#define ANACTRL_HDMIPLL_CTRL0 (0x0070 << 2)
|
||||
#define ANACTRL_HDMIPLL_CTRL1 (0x0071 << 2)
|
||||
#define ANACTRL_HDMIPLL_CTRL2 (0x0072 << 2)
|
||||
#define ANACTRL_HDMIPLL_CTRL3 (0x0073 << 2)
|
||||
#define ANACTRL_HDMIPLL_STS (0x0077 << 2)
|
||||
#define ANACTRL_HDMIPLL_VLOCK (0x0079 << 2)
|
||||
#define ANACTRL_HDMIPHY_CTRL0 (0x0080 << 2)
|
||||
#define ANACTRL_HDMIPHY_CTRL1 (0x0081 << 2)
|
||||
#define ANACTRL_HDMIPHY_CTRL2 (0x0082 << 2)
|
||||
#define ANACTRL_HDMIPHY_CTRL3 (0x0083 << 2)
|
||||
#define ANACTRL_HDMIPHY_CTRL4 (0x0084 << 2)
|
||||
#define ANACTRL_HDMIPHY_CTRL5 (0x0085 << 2)
|
||||
#define ANACTRL_HDMIPHY_STS (0x0086 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL0 (0x0090 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL1 (0x0091 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL2 (0x0092 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL3 (0x0093 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL4 (0x0094 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL5 (0x0095 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL6 (0x0096 << 2)
|
||||
#define ANACTRL_MIPICSI_CTRL7 (0x0097 << 2)
|
||||
#define ANACTRL_CSIPLL_CTRL0 (0x0098 << 2)
|
||||
#define ANACTRL_CSIPLL_CTRL1 (0x0099 << 2)
|
||||
#define ANACTRL_CSIPLL_CTRL2 (0x009a << 2)
|
||||
#define ANACTRL_CSIPLL_CTRL3 (0x009b << 2)
|
||||
#define ANACTRL_CSIPLL_STS (0x009c << 2)
|
||||
#define ANACTRL_VDAC_CTRL0 (0x00b0 << 2)
|
||||
#define ANACTRL_VDAC_CTRL1 (0x00b1 << 2)
|
||||
#define ANACTRL_POR_CTRL (0x00b6 << 2)
|
||||
#define ANACTRL_LOCK_BIT (0x00b8 << 2)
|
||||
#define ANACTRL_PROT_BIT (0x00b9 << 2)
|
||||
#define ANACTRL_DDR_LDO_CTRL (0x00d3 << 2)
|
||||
#define ANACTRL_MISC_PZQ_CTRL (0x00d4 << 2)
|
||||
#define ANACTRL_CHIP_TEST_STS0 (0x00e0 << 2)
|
||||
#define ANACTRL_CHIP_TEST_STS1 (0x00e1 << 2)
|
||||
#define ANACTRL_DSIPLL_CTRL0 (0x00f0 << 2)
|
||||
#define ANACTRL_DSIPLL_CTRL1 (0x00f1 << 2)
|
||||
#define ANACTRL_DSIPLL_CTRL2 (0x00f2 << 2)
|
||||
#define ANACTRL_DSIPLL_CTRL3 (0x00f3 << 2)
|
||||
#define ANACTRL_DSIPLL_STS (0x00f4 << 2)
|
||||
#define ANACTRL_MIPIDSI_CTRL0 (0x00f5 << 2)
|
||||
#define ANACTRL_MIPIDSI_CTRL1 (0x00f6 << 2)
|
||||
|
||||
#endif /* __S6_H */
|
||||
|
||||
@@ -7,27 +7,27 @@
|
||||
#define __S6_CLKC_H
|
||||
|
||||
#define CLKID_GP0_PLL 0
|
||||
#define CLKID_HIFI0_PLL 1
|
||||
#define CLKID_HIFI_PLL 1
|
||||
#define CLKID_HIFI1_PLL 2
|
||||
#define CLKID_FCLK50M_DIV 3
|
||||
#define CLKID_FCLK50M 4
|
||||
#define CLKID_FCLK_DIV2_DIV 5
|
||||
#define CLKID_FCLK_DIV2 6
|
||||
#define CLKID_FCLK_DIV2P5_DIV 7
|
||||
#define CLKID_FCLK_DIV2P5 8
|
||||
#define CLKID_FCLK_DIV3_DIV 9
|
||||
#define CLKID_FCLK_DIV3 10
|
||||
#define CLKID_FCLK_DIV4_DIV 11
|
||||
#define CLKID_FCLK_DIV4 12
|
||||
#define CLKID_FCLK_DIV5_DIV 13
|
||||
#define CLKID_FCLK_DIV5 14
|
||||
#define CLKID_FCLK_DIV7_DIV 15
|
||||
#define CLKID_FCLK_DIV7 16
|
||||
#define CLKID_MCLK_PLL 17
|
||||
#define CLKID_MCLK_PLL_CLK 18
|
||||
#define CLKID_MCLK0_DIV 19
|
||||
#define CLKID_MCLK0_DIV2 20
|
||||
#define CLKID_MCLK0 21
|
||||
#define CLKID_MCLK_PLL 3
|
||||
#define CLKID_MCLK_PLL_CLK 4
|
||||
#define CLKID_MCLK0_DIV 5
|
||||
#define CLKID_MCLK0_DIV2 6
|
||||
#define CLKID_MCLK0 7
|
||||
#define CLKID_FCLK50M_DIV 8
|
||||
#define CLKID_FCLK50M 9
|
||||
#define CLKID_FCLK_DIV2_DIV 10
|
||||
#define CLKID_FCLK_DIV2 11
|
||||
#define CLKID_FCLK_DIV2P5_DIV 12
|
||||
#define CLKID_FCLK_DIV2P5 13
|
||||
#define CLKID_FCLK_DIV3_DIV 14
|
||||
#define CLKID_FCLK_DIV3 15
|
||||
#define CLKID_FCLK_DIV4_DIV 16
|
||||
#define CLKID_FCLK_DIV4 17
|
||||
#define CLKID_FCLK_DIV5_DIV 18
|
||||
#define CLKID_FCLK_DIV5 19
|
||||
#define CLKID_FCLK_DIV7_DIV 20
|
||||
#define CLKID_FCLK_DIV7 21
|
||||
#define CLKID_RTC_DUAL_CLKIN 22
|
||||
#define CLKID_RTC_DUAL_DIV 23
|
||||
#define CLKID_RTC_DUAL_MUX 24
|
||||
@@ -51,12 +51,12 @@
|
||||
#define CLKID_CDAC_MUX 42
|
||||
#define CLKID_CDAC_DIV 43
|
||||
#define CLKID_CDAC 44
|
||||
#define CLKID_VIDEO_SRC0_MUX 45
|
||||
#define CLKID_VIDEO_SRC0_INPUT 46
|
||||
#define CLKID_VIDEO_SRC0_IN_MUX 45
|
||||
#define CLKID_VIDEO_SRC0_IN 46
|
||||
#define CLKID_VIDEO_SRC0_DIV 47
|
||||
#define CLKID_VIDEO_SRC0 48
|
||||
#define CLKID_VIDEO_SRC1_MUX 49
|
||||
#define CLKID_VIDEO_SRC1_INPUT 50
|
||||
#define CLKID_VIDEO_SRC1_IN_MUX 49
|
||||
#define CLKID_VIDEO_SRC1_IN 50
|
||||
#define CLKID_VIDEO_SRC1_DIV 51
|
||||
#define CLKID_VIDEO_SRC1 52
|
||||
#define CLKID_VIDEO0_DIV1 53
|
||||
@@ -266,67 +266,70 @@
|
||||
#define CLKID_SYS_DOS 257
|
||||
#define CLKID_SYS_VC9000E 258
|
||||
#define CLKID_SYS_MIPI_DSI 259
|
||||
#define CLKID_SYS_ETHPHY 260
|
||||
#define CLKID_SYS_ETH_PHY 260
|
||||
#define CLKID_SYS_AMFC 261
|
||||
#define CLKID_SYS_MALI 262
|
||||
#define CLKID_SYS_NNA 263
|
||||
#define CLKID_SYS_AOCPU 264
|
||||
#define CLKID_SYS_AUCPU 265
|
||||
#define CLKID_SYS_CEC 266
|
||||
#define CLKID_SYS_MIPI_DSI_PHY 267
|
||||
#define CLKID_SYS_SD_EMMC_A 268
|
||||
#define CLKID_SYS_SD_EMMC_B 269
|
||||
#define CLKID_SYS_SD_EMMC_C 270
|
||||
#define CLKID_SYS_SMARTCARD 271
|
||||
#define CLKID_SYS_ACODEC 272
|
||||
#define CLKID_SYS_MSR_CLK 273
|
||||
#define CLKID_SYS_IR_CTRL 274
|
||||
#define CLKID_SYS_AUDIO 275
|
||||
#define CLKID_SYS_ETH 276
|
||||
#define CLKID_SYS_UART_A 277
|
||||
#define CLKID_SYS_UART_B 278
|
||||
#define CLKID_SYS_UART_C 279
|
||||
#define CLKID_SYS_UART_D 280
|
||||
#define CLKID_SYS_UART_E 281
|
||||
#define CLKID_SYS_TS_PLL 282
|
||||
#define CLKID_SYS_CSI_DIG_CLKIN 283
|
||||
#define CLKID_SYS_GE2D 284
|
||||
#define CLKID_SYS_SPICC0 285
|
||||
#define CLKID_SYS_PCIE 286
|
||||
#define CLKID_SYS_USB 287
|
||||
#define CLKID_SYS_PCIE_PHY 288
|
||||
#define CLKID_SYS_I2C_M_A 289
|
||||
#define CLKID_SYS_I2C_M_B 290
|
||||
#define CLKID_SYS_I2C_M_C 291
|
||||
#define CLKID_SYS_I2C_M_D 292
|
||||
#define CLKID_SYS_I2C_M_E 293
|
||||
#define CLKID_SYS_I2C_M_F 294
|
||||
#define CLKID_SYS_HDMITX_APB 295
|
||||
#define CLKID_SYS_I2C_S_A 296
|
||||
#define CLKID_SYS_HDMI20_AES 297
|
||||
#define CLKID_SYS_MMC_APB 298
|
||||
#define CLKID_SYS_CSI2_HOST 299
|
||||
#define CLKID_SYS_CSI2_ADAPT 300
|
||||
#define CLKID_SYS_CPU_APB 301
|
||||
#define CLKID_SYS_DSPA 302
|
||||
#define CLKID_SYS_VPU_INTR 303
|
||||
#define CLKID_SYS_CSI2_PHY0 304
|
||||
#define CLKID_SYS_SAR_ADC 305
|
||||
#define CLKID_SYS_PWM_J 306
|
||||
#define CLKID_SYS_GIC 307
|
||||
#define CLKID_SYS_PWM_I 308
|
||||
#define CLKID_SYS_PWM_H 309
|
||||
#define CLKID_SYS_PWM_G 310
|
||||
#define CLKID_SYS_PWM_F 311
|
||||
#define CLKID_SYS_PWM_E 312
|
||||
#define CLKID_SYS_PWM_D 313
|
||||
#define CLKID_SYS_PWM_C 314
|
||||
#define CLKID_SYS_PWM_B 315
|
||||
#define CLKID_SYS_PWM_A 316
|
||||
#define CLKID_AXI_AO_NIC 317
|
||||
#define CLKID_AXI_DEV0_MMC 318
|
||||
#define CLKID_AXI_CPU_SRAM 319
|
||||
#define CLKID_SYS_ETH_MAC 264
|
||||
#define CLKID_SYS_AOCPU 265
|
||||
#define CLKID_SYS_AUCPU 266
|
||||
#define CLKID_SYS_CEC 267
|
||||
#define CLKID_SYS_MIPI_DSI_PHY 268
|
||||
#define CLKID_SYS_SD_EMMC_A 269
|
||||
#define CLKID_SYS_SD_EMMC_B 270
|
||||
#define CLKID_SYS_SD_EMMC_C 271
|
||||
#define CLKID_SYS_SMARTCARD 272
|
||||
#define CLKID_SYS_ACODEC 273
|
||||
#define CLKID_SYS_MSR_CLK 274
|
||||
#define CLKID_SYS_IR_CTRL 275
|
||||
#define CLKID_SYS_AUDIO 276
|
||||
#define CLKID_SYS_ETH 277
|
||||
#define CLKID_SYS_UART_A 278
|
||||
#define CLKID_SYS_UART_B 279
|
||||
#define CLKID_SYS_UART_C 280
|
||||
#define CLKID_SYS_UART_D 281
|
||||
#define CLKID_SYS_UART_E 282
|
||||
#define CLKID_SYS_TS_CORE 283
|
||||
#define CLKID_SYS_TS_PLL 284
|
||||
#define CLKID_SYS_CSI_DIG_CLKIN 285
|
||||
#define CLKID_SYS_GE2D 286
|
||||
#define CLKID_SYS_SPICC0 287
|
||||
#define CLKID_SYS_USB3DRD 288
|
||||
#define CLKID_SYS_USB2DRD 289
|
||||
#define CLKID_SYS_PCIE_PHY 290
|
||||
#define CLKID_SYS_PCIE_MAC 291
|
||||
#define CLKID_SYS_I2C_M_A 292
|
||||
#define CLKID_SYS_I2C_M_B 293
|
||||
#define CLKID_SYS_I2C_M_C 294
|
||||
#define CLKID_SYS_I2C_M_D 295
|
||||
#define CLKID_SYS_I2C_M_E 296
|
||||
#define CLKID_SYS_I2C_M_F 297
|
||||
#define CLKID_SYS_HDMITX_APB 298
|
||||
#define CLKID_SYS_I2C_S_A 299
|
||||
#define CLKID_SYS_HDMI20_AES 300
|
||||
#define CLKID_SYS_MMC_APB 301
|
||||
#define CLKID_SYS_CSI2_HOST 302
|
||||
#define CLKID_SYS_CSI2_ADAPT 303
|
||||
#define CLKID_SYS_CPU_APB 304
|
||||
#define CLKID_SYS_DSPA 305
|
||||
#define CLKID_SYS_VPU_INTR 306
|
||||
#define CLKID_SYS_CSI2_PHY0 307
|
||||
#define CLKID_SYS_SAR_ADC 308
|
||||
#define CLKID_SYS_PWM_J 309
|
||||
#define CLKID_SYS_GIC 310
|
||||
#define CLKID_SYS_PWM_I 311
|
||||
#define CLKID_SYS_PWM_H 312
|
||||
#define CLKID_SYS_PWM_G 313
|
||||
#define CLKID_SYS_PWM_F 314
|
||||
#define CLKID_SYS_PWM_E 315
|
||||
#define CLKID_SYS_PWM_D 316
|
||||
#define CLKID_SYS_PWM_C 317
|
||||
#define CLKID_SYS_PWM_B 318
|
||||
#define CLKID_SYS_PWM_A 319
|
||||
#define CLKID_AXI_AO_NIC 320
|
||||
#define CLKID_AXI_DEV0_MMC 321
|
||||
#define CLKID_AXI_CPU_SRAM 322
|
||||
|
||||
#define NR_CLKS 320
|
||||
#define NR_CLKS 323
|
||||
|
||||
#endif /* __S6_CLKC_H */
|
||||
|
||||
Reference in New Issue
Block a user