shinys000114/kernel_common_drivers
1
0
Fork 0
mirror of https://github.com/hardkernel/kernel_common_drivers.git synced 2026-06-25 12:03:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

audio: set arc/earc config dynamic [1/1]

Browse Source 
PD#SWPL-146446

Problem:
TV change earc mode, but soundbar always work on one mode

Solution:
1.revert change "eARC rx earc mode sample ctrl" as it is
effect earc discovery
2.set arc/earc config dynamic

Verify:
sm1

Change-Id: Ie9b48cb7173cafa0b4a99a42703ba1ee5df1dd56
Signed-off-by: jian zhou <jian.zhou@amlogic.com>
This commit is contained in:
jian zhou
2023-11-17 20:06:37 +08:00
committed by gerrit autosubmit
parent 90c249a79b
commit 446ee162f9
3 changed files with 49 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sound/soc/amlogic/auge/earc.c
+10
View File
@@ -398,12 +398,22 @@ static void earcrx_update_attend_event(struct earc *p_earc,
bool is_earc, bool state)
{
if (state) {
unsigned long flags;
if (is_earc) {
spin_lock_irqsave(&p_earc->rx_lock, flags);
if (p_earc->rx_dmac_clk_on)
earcrx_set_dmac_sync_ctrl(p_earc->rx_dmac_map, true, true);
spin_unlock_irqrestore(&p_earc->rx_lock, flags);
extcon_set_state_sync(p_earc->rx_edev,
EXTCON_EARCRX_ATNDTYP_ARC, false);
extcon_set_state_sync(p_earc->rx_edev,
EXTCON_EARCRX_ATNDTYP_EARC, state);
} else {
spin_lock_irqsave(&p_earc->rx_lock, flags);
if (p_earc->rx_dmac_clk_on)
earcrx_set_dmac_sync_ctrl(p_earc->rx_dmac_map, false, true);
spin_unlock_irqrestore(&p_earc->rx_lock, flags);
extcon_set_state_sync(p_earc->rx_edev,
EXTCON_EARCRX_ATNDTYP_ARC, state);
extcon_set_state_sync(p_earc->rx_edev,
sound/soc/amlogic/auge/earc_hw.c
+38 -27
View File
@@ -240,12 +240,6 @@ void earcrx_dmac_init(struct regmap *top_map,
(0x0 << 0) /* arcrx_dmac_sync afifo_overflow */
);
mmio_write(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
(1 << 16) | /* reg_ana_buf_data_sel_en */
(3 << 12) | /* reg_ana_buf_data_sel */
(7 << 8) | /* reg_ana_clr_cnt */
(7 << 4) /* reg_ana_set_cnt */
);
mmio_write(dmac_map, EARCRX_DMAC_UBIT_CTRL0,
(47 << 16) | /* reg_fifo_thd */
(1 << 12) | /* reg_user_lr */
@@ -712,20 +706,47 @@ void earcrx_reset(struct regmap *dmac_map)
mmio_update_bits(dmac_map, EARCRX_DMAC_TOP_CTRL0, 1 << 30, 0x0 << 30);
}
void earcrx_set_dmac_sync_ctrl(struct regmap *dmac_map, bool is_earc, bool enable)
{
if (is_earc) {
mmio_update_bits(dmac_map,
EARCRX_SPDIFIN_SAMPLE_CTRL0,
0x1 << 31, /* reg_work_enable */
0);
mmio_write(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
(1 << 16) | /* reg_ana_buf_data_sel_en */
(3 << 12) | /* reg_ana_buf_data_sel */
(7 << 8) | /* reg_ana_clr_cnt */
(7 << 4)); /* reg_ana_set_cnt */
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
1 << 30, /* reg_rst_afifo_out_n */
enable << 30);
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
1 << 29, /* reg_rst_afifo_in_n */
enable << 29);
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
1 << 31, /* reg_work_en */
enable << 31);
} else {
mmio_update_bits(dmac_map,
EARCRX_SPDIFIN_SAMPLE_CTRL0,
0x1 << 31, /* reg_work_enable */
enable << 31);
mmio_write(dmac_map, EARCRX_DMAC_SYNC_CTRL0, 0x0);
}
}
void earcrx_enable(struct regmap *cmdc_map,
struct regmap *dmac_map, bool enable)
{
enum attend_type type = earcrx_cmdc_get_attended_type(cmdc_map);
if (enable) {
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
1 << 30, /* reg_rst_afifo_out_n */
1 << 30);
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
1 << 29, /* reg_rst_afifo_in_n */
0x1 << 29);
mmio_update_bits(dmac_map, EARCRX_ERR_CORRECT_CTRL0,
1 << 29, /* reg_rst_afifo_out_n */
1 << 29
@@ -735,10 +756,6 @@ void earcrx_enable(struct regmap *cmdc_map,
1 << 28 /* reg_rst_afifo_in_n */
);
} else {
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
0x3 << 29,
0x0 << 29);
mmio_update_bits(dmac_map, EARCRX_ERR_CORRECT_CTRL0,
0x3 << 28, 0x0 << 28);
}
@@ -747,19 +764,13 @@ void earcrx_enable(struct regmap *cmdc_map,
/* mute block check */
earcrx_mute_block_enable(dmac_map, true);
mmio_update_bits(dmac_map, EARCRX_DMAC_SYNC_CTRL0,
1 << 31, /* reg_work_en */
enable << 31);
earcrx_set_dmac_sync_ctrl(dmac_map, true, enable);
} else if (type == ATNDTYP_ARC) {
/* mute block check */
earcrx_mute_block_enable(dmac_map, false);
mmio_update_bits(dmac_map,
EARCRX_SPDIFIN_SAMPLE_CTRL0,
0x1 << 31, /* reg_work_enable */
enable << 31);
mmio_write(dmac_map, EARCRX_DMAC_SYNC_CTRL0, 0x0);
earcrx_set_dmac_sync_ctrl(dmac_map, false, enable);
}
mmio_update_bits(dmac_map, EARCRX_DMAC_UBIT_CTRL0,
sound/soc/amlogic/auge/earc_hw.h
+1
View File
@@ -266,6 +266,7 @@ int earcrx_dmac_get_irqs(struct regmap *top_map);
int earcrx_dmac_get_mask(struct regmap *top_map);
bool earcrx_pll_dmac_valid(struct regmap *top_map);
void earcrx_reset(struct regmap *dmac_map);
void earcrx_set_dmac_sync_ctrl(struct regmap *dmac_map, bool is_earc, bool enable);
void earcrx_enable(struct regmap *cmdc_map,
struct regmap *dmac_map, bool enable);
void earctx_cmdc_int_mask(struct regmap *top_map);