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saradc: test channel is no longer fixed to channel 7 [1/3]

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PD#SWPL-152407

Problem:
Channel 7 is no longer fixed as a test channel, so some
variables need to be renamed.
(S7 Silicon Bringup)

Solution:
Some variables have been renamed in the following format:
- chan7_mux   -> test_input
- chan7_vol   -> test_vol
- set_ch7_mux -> set_test_input

Verify:
S7/BH201

Change-Id: Ia9141b9e16d42c60b520a8a6b32cdbb22f29db41
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
This commit is contained in:
Huqiang Qin
2024-01-12 11:28:48 +08:00
committed by gerrit autosubmit
parent 6a44d008d6
commit 47f1219af4
6 changed files with 46 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/iio/adc/meson_saradc.c
+22 -22
View File
@@ -157,15 +157,15 @@
#define SAR_ADC_DEF_VREF 1800000 /* uV */
static const char * const chan7_vol[] = {
static const char * const test_vol[] = {
"gnd",
"vdd/4",
"vdd/2",
"vdd*3/4",
"vdd",
"ch7_input",
"ch7_input",
"ch7_input",
"chan_input",
"chan_input",
"chan_input",
};
enum meson_sar_adc_filter_mode {
@@ -974,7 +974,7 @@ static int meson_sar_adc_calib(struct iio_dev *indio_dev)
nominal0 = (1 << priv->param->resolution) / 4;
nominal1 = (1 << priv->param->resolution) * 3 / 4;
priv->param->dops->set_ch7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
priv->param->dops->set_test_input(indio_dev, TEST_MUX_VDD_DIV4);
usleep_range(10, 20);
ret = meson_sar_adc_get_sample(indio_dev,
&indio_dev->channels[7],
@@ -983,7 +983,7 @@ static int meson_sar_adc_calib(struct iio_dev *indio_dev)
if (ret < 0)
goto out;
priv->param->dops->set_ch7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
priv->param->dops->set_test_input(indio_dev, TEST_MUX_VDD_MUL3_DIV4);
usleep_range(10, 20);
ret = meson_sar_adc_get_sample(indio_dev,
&indio_dev->channels[7],
@@ -1003,7 +1003,7 @@ static int meson_sar_adc_calib(struct iio_dev *indio_dev)
MILLION);
ret = 0;
out:
priv->param->dops->set_ch7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
priv->param->dops->set_test_input(indio_dev, TEST_MUX_CHANN_INPUT);
return ret;
}
@@ -1213,8 +1213,8 @@ static const struct iio_buffer_setup_ops meson_buffer_setup_ops = {
};
#endif
static ssize_t chan7_mux_show(struct device *dev, struct device_attribute *attr,
char *buf)
static ssize_t test_input_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
@@ -1222,16 +1222,16 @@ static ssize_t chan7_mux_show(struct device *dev, struct device_attribute *attr,
int i;
len = sprintf(buf, "current: [%d]%s\n\n",
priv->chan7_mux_sel, chan7_vol[priv->chan7_mux_sel]);
for (i = 0; i < ARRAY_SIZE(chan7_vol); i++)
len += sprintf(buf + len, "%d: %s\n", i, chan7_vol[i]);
priv->test_input_sel, test_vol[priv->test_input_sel]);
for (i = 0; i < ARRAY_SIZE(test_vol); i++)
len += sprintf(buf + len, "%d: %s\n", i, test_vol[i]);
return len;
}
static ssize_t chan7_mux_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
static ssize_t test_input_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
@@ -1239,7 +1239,7 @@ static ssize_t chan7_mux_store(struct device *dev,
if (kstrtoint(buf, 0, &val) != 0)
return -EINVAL;
if (val >= ARRAY_SIZE(chan7_vol))
if (val >= ARRAY_SIZE(test_vol))
return -EINVAL;
if (meson_sar_adc_pm_runtime_supported(indio_dev)) {
@@ -1247,7 +1247,7 @@ static ssize_t chan7_mux_store(struct device *dev,
return -EINVAL;
}
priv->param->dops->set_ch7_mux(indio_dev, val);
priv->param->dops->set_test_input(indio_dev, val);
if (meson_sar_adc_pm_runtime_supported(indio_dev)) {
pm_runtime_mark_last_busy(indio_dev->dev.parent);
@@ -1257,11 +1257,11 @@ static ssize_t chan7_mux_store(struct device *dev,
return count;
}
static IIO_DEVICE_ATTR(chan7_mux, 0644,
chan7_mux_show, chan7_mux_store, -1);
static IIO_DEVICE_ATTR(test_input, 0644,
test_input_show, test_input_store, -1);
static struct attribute *meson_sar_adc_attrs[] = {
&iio_dev_attr_chan7_mux.dev_attr.attr,
&iio_dev_attr_test_input.dev_attr.attr,
NULL, /*need to terminate the list of attributes by NULL*/
};
@@ -1435,7 +1435,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
priv->param = match_param;
if (!match_param->dops->extra_init || !match_param->dops->set_ch7_mux ||
if (!match_param->dops->extra_init || !match_param->dops->set_test_input ||
!match_param->dops->read_fifo || !match_param->dops->enable_chnl ||
!match_param->dops->read_chnl) {
dev_err(&pdev->dev, "necessary operations not supported\n");
@@ -1712,7 +1712,7 @@ static int __maybe_unused meson_sar_adc_runtime_resume(struct device *dev)
if (ret)
return ret;
priv->param->dops->set_ch7_mux(indio_dev, priv->chan7_mux_sel);
priv->param->dops->set_test_input(indio_dev, priv->test_input_sel);
return 0;
}
drivers/iio/adc/meson_saradc.h
+10 -10
View File
@@ -18,13 +18,13 @@ enum meson_sar_adc_vref_sel {
VDDA_AS_VREF = 1,
};
enum meson_sar_adc_chan7_mux_sel {
CHAN7_MUX_VSS = 0x0,
CHAN7_MUX_VDD_DIV4 = 0x1,
CHAN7_MUX_VDD_DIV2 = 0x2,
CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
CHAN7_MUX_VDD = 0x4,
CHAN7_MUX_CH7_INPUT = 0x7,
enum meson_sar_adc_test_input_sel {
TEST_MUX_VSS = 0x0,
TEST_MUX_VDD_DIV4 = 0x1,
TEST_MUX_VDD_DIV2 = 0x2,
TEST_MUX_VDD_MUL3_DIV4 = 0x3,
TEST_MUX_VDD = 0x4,
TEST_MUX_CHANN_INPUT = 0x7,
};
enum meson_sar_adc_sampling_mode {
@@ -35,8 +35,8 @@ enum meson_sar_adc_sampling_mode {
struct meson_sar_adc_diff_ops {
int (*extra_init)(struct iio_dev *indio_dev);
void (*set_ch7_mux)(struct iio_dev *indio_dev,
enum meson_sar_adc_chan7_mux_sel sel);
void (*set_test_input)(struct iio_dev *indio_dev,
enum meson_sar_adc_test_input_sel sel);
int (*read_fifo)(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan, bool chk_channel);
void (*enable_chnl)(struct iio_dev *indio_dev, bool en);
@@ -119,7 +119,7 @@ struct meson_sar_adc_priv {
int ticks_per_period;
int active_channel_cnt;
u8 *datum_buf;
u8 chan7_mux_sel;
u8 test_input_sel;
u32 continuous_sample_count;
struct completion done;
u32 *continuous_sample_buffer;
drivers/iio/adc/meson_saradc_c2.c
+4 -4
View File
@@ -141,8 +141,8 @@ static int meson_c2_sar_adc_extra_init(struct iio_dev *indio_dev)
return 0;
}
static void meson_c2_sar_adc_set_ch7_mux(struct iio_dev *indio_dev,
enum meson_sar_adc_chan7_mux_sel sel)
static void meson_c2_sar_adc_set_test_input(struct iio_dev *indio_dev,
enum meson_sar_adc_test_input_sel sel)
{
unsigned int regval;
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
@@ -151,7 +151,7 @@ static void meson_c2_sar_adc_set_ch7_mux(struct iio_dev *indio_dev,
regmap_update_bits(priv->regmap, MESON_C2_SAR_ADC_CHX_CTRL1(7),
MESON_C2_SAR_ADC_CHX_CTRL1_IN_CTRL_MASK, regval);
priv->chan7_mux_sel = sel;
priv->test_input_sel = sel;
usleep_range(10, 20);
}
@@ -309,7 +309,7 @@ static int meson_c2_sar_adc_tuning_clock(struct iio_dev *indio_dev,
static const struct meson_sar_adc_diff_ops meson_c2_diff_ops = {
.extra_init = meson_c2_sar_adc_extra_init,
.set_ch7_mux = meson_c2_sar_adc_set_ch7_mux,
.set_test_input = meson_c2_sar_adc_set_test_input,
.read_fifo = meson_c2_sar_adc_read_fifo,
.enable_chnl = meson_c2_sar_adc_enable_chnl,
.read_chnl = meson_c2_sar_adc_read_chnl,
drivers/iio/adc/meson_saradc_m8.c
+7 -7
View File
@@ -6,7 +6,7 @@
#include "meson_saradc.h"
#define MESON_SAR_ADC_REG3 0x0c
#define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
#define MESON_SAR_ADC_REG3_CTRL_TEST_MUX_SEL_MASK GENMASK(25, 23)
#define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
#define MESON_SAR_ADC_FIFO_RD 0x18
@@ -182,17 +182,17 @@ static int meson_m8_sar_adc_extra_init(struct iio_dev *indio_dev)
return 0;
}
void meson_m8_sar_adc_set_ch7_mux(struct iio_dev *indio_dev,
enum meson_sar_adc_chan7_mux_sel sel)
void meson_m8_sar_adc_set_test_input(struct iio_dev *indio_dev,
enum meson_sar_adc_test_input_sel sel)
{
unsigned int regval;
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_TEST_MUX_SEL_MASK, sel);
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
MESON_SAR_ADC_REG3_CTRL_TEST_MUX_SEL_MASK, regval);
priv->chan7_mux_sel = sel;
priv->test_input_sel = sel;
usleep_range(10, 20);
}
@@ -295,7 +295,7 @@ static void meson_m8_sar_adc_select_temp(struct iio_dev *indio_dev,
static const struct meson_sar_adc_diff_ops meson_m8_diff_ops = {
.extra_init = meson_m8_sar_adc_extra_init,
.set_ch7_mux = meson_m8_sar_adc_set_ch7_mux,
.set_test_input = meson_m8_sar_adc_set_test_input,
.read_fifo = meson_m8_sar_adc_read_fifo,
.enable_chnl = meson_m8_sar_adc_enable_chnl,
.read_chnl = meson_m8_sar_adc_read_chnl,
drivers/iio/adc/meson_saradc_m8.h
+2 -2
View File
@@ -5,8 +5,8 @@
#include "meson_saradc.h"
void meson_m8_sar_adc_set_ch7_mux(struct iio_dev *indio_dev,
enum meson_sar_adc_chan7_mux_sel sel);
void meson_m8_sar_adc_set_test_input(struct iio_dev *indio_dev,
enum meson_sar_adc_test_input_sel sel);
int meson_m8_sar_adc_read_fifo(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
bool chk_channel);
drivers/iio/adc/meson_saradc_s7.c
+1 -1
View File
@@ -152,7 +152,7 @@ without_pd:
static const struct meson_sar_adc_diff_ops meson_s7_diff_ops = {
.extra_init = meson_s7_sar_adc_extra_init,
.set_ch7_mux = meson_m8_sar_adc_set_ch7_mux,
.set_test_input = meson_m8_sar_adc_set_test_input,
.read_fifo = meson_m8_sar_adc_read_fifo,
.enable_chnl = meson_m8_sar_adc_enable_chnl,
.read_chnl = meson_m8_sar_adc_read_chnl,