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ddr_tool: s7 dmc bring up [1/1]

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PD#SWPL-152397

Problem:
1. fix ddr freq reg
2. add ddr priority support

Solution:
1. fix ddr freq reg
2. add ddr priority support

Verify:
s7

Change-Id: I2e8af4b2f1b8a9bb820db52f5fa6045da65ebed3
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
This commit is contained in:
qinglin.li
2024-01-11 15:42:45 +08:00
committed by pengzhao.liu
parent 67bc8f3603
commit 492feeaaba
2 changed files with 112 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-s7.dtsi
+1 -1
View File
@@ -1498,7 +1498,7 @@
compatible = "amlogic,ddr-bandwidth-s7";
status = "okay";
reg = <0 0xfe036000 0 0x400
0 0xfe036000 0 0x100>;
0 0xfe0368a8 0 0x4>;
interrupts = <0 78 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ddr_bandwidth";
};
drivers/memory_debug/ddr_tool/ddr_priority.c
+111
View File
@@ -1180,6 +1180,113 @@ static struct ddr_priority ddr_priority_t3[] __initdata = {
.w_offset = 0, .w_bit_s = 0, .w_width = 0,
.r_offset = 0, .r_bit_s = 0, .r_width = 0 },
};
static struct ddr_priority ddr_priority_s7[] __initdata = {
{ .port_id = 0, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0x80 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0x80 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 1, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0x84 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0x84 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 2, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0x88 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0x88 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 4, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0x90 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0x90 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 6, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0x98 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0x98 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 7, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0x9c << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0x9c << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 8, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0xac << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0xac << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 10, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0xb4 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0xb4 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 11, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0xb8 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0xb8 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 12, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0xbc << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0xbc << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 13, .reg_base = 0xfe036000,
.reg_mode = 0, .reg_config = 0x8000,
.w_offset = (0xc0 << 2), .w_bit_s = 16, .w_width = 0xf,
.r_offset = (0xc0 << 2), .r_bit_s = 16, .r_width = 0xf },
{ .port_id = 32, .reg_base = 0xffe46000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 33, .reg_base = 0xffe47000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 34, .reg_base = 0xffe48000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 39, .reg_base = 0xffe4b000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 36, .reg_base = 0xffe45000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 39, .reg_base = 0xffe4b000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 40, .reg_base = 0x0,
.reg_mode = 0, .reg_config = 0x0,
.w_offset = 0x0, .w_bit_s = 0, .w_width = 0x0,
.r_offset = 0x0, .r_bit_s = 0, .r_width = 0x0 },
{ .port_id = 41, .reg_base = 0xffe49000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 42, .reg_base = 0xffe4a000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
{ .port_id = 43, .reg_base = 0xffe4b000,
.reg_mode = 1, .reg_config = 0x0,
.w_offset = 0x100, .w_bit_s = 0, .w_width = 0xf,
.r_offset = 0x100, .r_bit_s = 0, .r_width = 0xf },
};
#endif
static struct ddr_priority ddr_priority_s1a[] __initdata = {
{ .port_id = 0, .reg_base = 0xfe036000,
@@ -1268,6 +1375,10 @@ int __init ddr_find_port_priority(int cpu_type, struct ddr_priority **desc)
*desc = ddr_priority_t3;
desc_size = ARRAY_SIZE(ddr_priority_t3);
break;
case DMC_TYPE_S7:
*desc = ddr_priority_s7;
desc_size = ARRAY_SIZE(ddr_priority_s7);
break;
#endif
case DMC_TYPE_S1A:
*desc = ddr_priority_s1a;