mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
Merge "vpu_security: fix vpu security not set for 2slice [1/1]" into amlogic-5.15-dev
This commit is contained in:
@@ -274,6 +274,10 @@ static void secure_reg_update(struct vpu_secure_ins *ins,
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reg_size = ARRAY_SIZE(reg_v5);
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reg_item = ®_v5[0];
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}
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if (log_level & 1)
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pr_info("line=%d, vpu secure bit 0x%x, reg_size=0x%x, bit_changed=0x%x\n",
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__LINE__, change->current_val, reg_size,
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change->bit_changed);
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/* work through the array and write bit(s) */
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for (i = 0; i < reg_size; i++) {
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@@ -281,8 +285,14 @@ static void secure_reg_update(struct vpu_secure_ins *ins,
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en = BIT(i) & change->current_val;
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reg_val = en ? reg_item[i].en :
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(!reg_item[i].en);
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if (!reg_item[i].reg)
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continue;
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if (log_level & 1)
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pr_info("line=%d, vpu secure bit 0x%x, en=%d, reg_val=0x%x, reg=0x%x\n",
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__LINE__, change->current_val, en,
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reg_val,
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reg_item[i].reg);
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ins->reg_wr_op[vpp_index](reg_item[i].reg,
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reg_val,
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reg_item[i].start,
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@@ -332,7 +342,7 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
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value = osd_secure[vpp_index] |
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video_secure[vpp_index];
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ins->secure_enable = 1;
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ins->secure_status = value;
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osd_secure_en[vpp_index] = 1;
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} else {
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/* OSD none secure */
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@@ -340,9 +350,25 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
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value = osd_secure[vpp_index] |
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video_secure[vpp_index];
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ins->secure_enable = 0;
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ins->secure_status = value;
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osd_secure_en[vpp_index] = 0;
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}
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if (version == VPU_SEC_V4) {
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u32 temp;
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if (value & VD1_INPUT_SECURE) {
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if (is_meson_t3x_cpu())
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temp = VD1_SLICE1_SECURE;
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else
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temp = VD1_SLICE1_SECURE |
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VD1_SLICE2_SECURE |
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VD1_SLICE3_SECURE;
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value |= temp;
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if (log_level & 4)
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pr_info("line=%d,secure_enable=%d module=%d value=0x%x\n",
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__LINE__, module, ins->secure_enable, value);
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}
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}
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ins->secure_status = value;
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break;
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case VIDEO_MODULE:
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if ((secure_src & VD2_FGRAIN_SECURE) ||
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@@ -356,31 +382,33 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
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video_secure[vpp_index] = secure_src;
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value = video_secure[vpp_index] |
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osd_secure[vpp_index];
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if (version == VPU_SEC_V4) {
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u32 temp;
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if (value & VD1_INPUT_SECURE) {
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if (is_meson_t3x_cpu())
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temp = VD1_SLICE1_SECURE;
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else
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temp = VD1_SLICE1_SECURE |
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VD1_SLICE2_SECURE |
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VD1_SLICE3_SECURE;
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value |= temp;
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}
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}
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ins->secure_enable = 1;
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ins->secure_status = value;
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video_secure_en[vpp_index] = 1;
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} else {
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/* video module secure */
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/* video module none secure */
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video_secure[vpp_index] = secure_src;
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value = video_secure[vpp_index] |
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osd_secure[vpp_index];
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ins->secure_enable = 0;
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ins->secure_status = value;
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video_secure_en[vpp_index] = 0;
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}
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if (version == VPU_SEC_V4) {
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u32 temp;
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if (value & VD1_INPUT_SECURE) {
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if (is_meson_t3x_cpu())
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temp = VD1_SLICE1_SECURE;
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else
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temp = VD1_SLICE1_SECURE |
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VD1_SLICE2_SECURE |
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VD1_SLICE3_SECURE;
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value |= temp;
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if (log_level & 4)
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pr_info("line=%d,secure_enable=%d module=%d value=0x%x\n",
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__LINE__, module, ins->secure_enable, value);
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}
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}
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ins->secure_status = value;
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break;
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case DI_MODULE:
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break;
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@@ -424,14 +452,19 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
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change.bit_changed =
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value ^ value_save[vpp_index];
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change.current_val = value;
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if (log_level & 1)
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pr_info("line=%d,module=%d value=0x%x, value_save=0x%x, bit_changed=0x%x\n",
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__LINE__, module, value, value_save[vpp_index],
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change.bit_changed);
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secure_reg_update(ins, &change, vpp_index);
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secure_update = 1;
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}
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value_save[vpp_index] = value;
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}
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if (log_level >= 2)
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pr_info("vpu secure bit 0x%x\n", value);
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if (log_level & 2)
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pr_info("module=%d ,vpu secure bit 0x%x\n",
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module, value);
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secure_cfg = value_save[VPP_TOP] |
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value_save[VPP_TOP_1] |
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@@ -13727,6 +13727,8 @@ void video_secure_set(u8 vpp_index)
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u32 secure_src = 0;
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u32 secure_enable = 0;
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u32 fg_secure_enable = 0;
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u32 video_enable = 0;
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static bool disable_update = true;
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struct video_layer_s *layer = NULL;
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for (i = 0; i < MAX_VD_LAYERS; i++) {
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@@ -13763,8 +13765,18 @@ void video_secure_set(u8 vpp_index)
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else if (layer->layer_id == 1)
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secure_src |= VD2_FGRAIN_SECURE;
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}
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video_enable |= layer->enabled;
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}
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if (video_enable) {
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secure_config(VIDEO_MODULE, secure_src, vpp_index);
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disable_update = true;
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} else {
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if (disable_update) {
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secure_config(VIDEO_MODULE, secure_src, vpp_index);
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disable_update = false;
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}
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}
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secure_config(VIDEO_MODULE, secure_src, vpp_index);
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#endif
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}
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@@ -8732,6 +8732,8 @@ void video_secure_set(u8 vpp_index)
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int i;
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u32 secure_src = 0;
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u32 secure_enable = 0;
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u32 video_enable = 0;
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static bool disable_update = true;
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struct video_layer_s *layer = NULL;
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for (i = 0; i < MAX_VD_LAYERS; i++) {
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@@ -8756,8 +8758,18 @@ void video_secure_set(u8 vpp_index)
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else if (layer->layer_id == 2)
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secure_src |= VD3_INPUT_SECURE;
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}
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video_enable |= layer->enabled;
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}
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secure_config(VIDEO_MODULE, secure_src, vpp_index);
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if (video_enable) {
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secure_config(VIDEO_MODULE, secure_src, vpp_index);
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disable_update = true;
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} else {
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if (disable_update) {
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secure_config(VIDEO_MODULE, secure_src, vpp_index);
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disable_update = false;
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}
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}
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#endif
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}
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