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g12b/sm1: add clock tree [1/1]

Browse Source 
PD#SWPL-104283

Problem:
porting to kernel5.15

Solution:
fixed

Verify:
w400/ac200

Change-Id: I858a7ffd12d64dcc8e1e8082977814de070052d0
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
This commit is contained in:
Chuan Liu
2022-12-30 20:55:12 +08:00
committed by yao zhang1
parent 8a425a895e
commit 51c61d4047
16 changed files with 8473 additions and 892 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/g12b_a311d_w400.dts
+64 -64
View File
@@ -193,14 +193,14 @@
compatible = "amlogic, cvbsout-g12b";
dev_name = "cvbsout";
status = "disable"
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_DAC_CLK>;
clock-names = "venci_top_gate",
"venci_0_gate",
"venci_1_gate",
"vdac_clk_gate";
//clocks = <&clkc CLKID_VCLK2_ENCI
// &clkc CLKID_VCLK2_VENCI0
// &clkc CLKID_VCLK2_VENCI1
// &clkc CLKID_DAC_CLK>;
//clock-names = "venci_top_gate",
// "venci_0_gate",
// "venci_1_gate",
// "vdac_clk_gate";
/* performance: reg_address, reg_value */
/* g12b */
@@ -276,10 +276,10 @@
interrupts = <0 46 1
0 40 1>;
interrupt-names = "pre_irq", "post_irq";
clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
<&clkc CLKID_VPU_CLKB_COMP>;
clock-names = "vpu_clkb_tmp_composite",
"vpu_clkb_composite";
//clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
// <&clkc CLKID_VPU_CLKB_COMP>;
//clock-names = "vpu_clkb_tmp_composite",
// "vpu_clkb_composite";
clock-range = <334 667>;
/* buffer-size = <3621952>;(yuv422 8bit) */
buffer-size = <4074560>;/*yuv422 fullpack*/
@@ -592,14 +592,14 @@
};
audiolocker: locker {
compatible = "amlogic, audiolocker";
clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT
&clkaudio CLKID_AUDIO_LOCKER_IN
&clkaudio CLKID_AUDIO_MCLK_D
&clkaudio CLKID_AUDIO_MCLK_E
&clkc CLKID_MPLL1
&clkc CLKID_MPLL2>;
clock-names = "lock_out", "lock_in", "out_src",
"in_src", "out_calc", "in_ref";
//clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT
// &clkaudio CLKID_AUDIO_LOCKER_IN
// &clkaudio CLKID_AUDIO_MCLK_D
// &clkaudio CLKID_AUDIO_MCLK_E
// &clkc CLKID_MPLL1
// &clkc CLKID_MPLL2>;
//clock-names = "lock_out", "lock_in", "out_src",
// "in_src", "out_calc", "in_ref";
interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "irq";
frequency = <49000000>; /* pll */
@@ -711,8 +711,8 @@
sensor-name = "imx290"; /*imx290;os08a10;imx227*/
pinctrl-names="default";
pinctrl-0=<&clk12_24_z_pins>;
clocks = <&clkc CLKID_24M>;
clock-names = "g12a_24m";
//clocks = <&clkc CLKID_24M>;
//clock-names = "g12a_24m";
reset = <&gpio GPIOZ_12 GPIO_ACTIVE_HIGH>;
ir_cut_gpio = <&gpio GPIOZ_11 GPIO_ACTIVE_HIGH
&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
@@ -853,9 +853,9 @@
dai-tdm-lane-slot-mask-in = <0 1>;
dai-tdm-oe-lane-slot-mask-out = <1 0>;
dai-tdm-clk-sel = <0>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_A
&clkc CLKID_MPLL0>;
clock-names = "mclk", "clk_srcpll";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_A
// &clkc CLKID_MPLL0>;
//clock-names = "mclk", "clk_srcpll";
pinctrl-names = "tdm_pins";
pinctrl-0 = <&tdmout_a &tdmin_a>;
};
@@ -866,12 +866,12 @@
dai-tdm-lane-slot-mask-in = <0 1 0 0>;
dai-tdm-lane-slot-mask-out = <1 0 0 0>;
dai-tdm-clk-sel = <1>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_B
&clkc CLKID_MPLL1
&clkc CLKID_MPLL0
&clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>;
clock-names = "mclk", "clk_srcpll",
"samesource_srcpll", "samesource_clk";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_B
// &clkc CLKID_MPLL1
// &clkc CLKID_MPLL0
// &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>;
//clock-names = "mclk", "clk_srcpll",
// "samesource_srcpll", "samesource_clk";
pinctrl-names = "tdm_pins";
pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>;
/*
@@ -892,9 +892,9 @@
#dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>;
#dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>;
dai-tdm-clk-sel = <2>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_C
&clkc CLKID_MPLL2>;
clock-names = "mclk", "clk_srcpll";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_C
// &clkc CLKID_MPLL2>;
//clock-names = "mclk", "clk_srcpll";
pinctrl-names = "tdm_pins";
pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>;
};
@@ -905,9 +905,9 @@
#sound-dai-cells = <0>;
dai-tdm-lane-slot-mask-out = <1 1 1 1>;
dai-tdm-clk-sel = <2>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_C
&clkc CLKID_MPLL2>;
clock-names = "mclk", "clk_srcpll";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_C
// &clkc CLKID_MPLL2>;
//clock-names = "mclk", "clk_srcpll";
i2s2hdmi = <1>;
@@ -917,14 +917,14 @@
aml_spdif: spdif {
compatible = "amlogic, g12a-snd-spdif-a";
#sound-dai-cells = <0>;
clocks = <&clkc CLKID_MPLL0
&clkc CLKID_FCLK_DIV4
&clkaudio CLKID_AUDIO_SPDIFIN
&clkaudio CLKID_AUDIO_SPDIFOUT
&clkaudio CLKID_AUDIO_SPDIFIN_CTRL
&clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>;
clock-names = "sysclk", "fixed_clk", "gate_spdifin",
"gate_spdifout", "clk_spdifin", "clk_spdifout";
//clocks = <&clkc CLKID_MPLL0
// &clkc CLKID_FCLK_DIV4
// &clkaudio CLKID_AUDIO_SPDIFIN
// &clkaudio CLKID_AUDIO_SPDIFOUT
// &clkaudio CLKID_AUDIO_SPDIFIN_CTRL
// &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>;
//clock-names = "sysclk", "fixed_clk", "gate_spdifin",
// "gate_spdifout", "clk_spdifin", "clk_spdifout";
interrupts =
<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
@@ -938,26 +938,26 @@
aml_spdif_b: spdif_b {
compatible = "amlogic, g12a-snd-spdif-b";
#sound-dai-cells = <0>;
clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
&clkaudio CLKID_AUDIO_SPDIFOUTB
&clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>;
clock-names = "sysclk",
"gate_spdifout", "clk_spdifout";
//clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
// &clkaudio CLKID_AUDIO_SPDIFOUTB
// &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>;
//clock-names = "sysclk",
// "gate_spdifout", "clk_spdifout";
status = "disabled";
};
aml_pdm: pdm {
compatible = "amlogic, g12a-snd-pdm";
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
"sysclk_srcpll",
"dclk_srcpll",
"pdm_dclk",
"pdm_sysclk";
//clocks = <&clkaudio CLKID_AUDIO_PDM
// &clkc CLKID_FCLK_DIV3
// &clkc CLKID_MPLL3
// &clkaudio CLKID_AUDIO_PDMIN0
// &clkaudio CLKID_AUDIO_PDMIN1>;
//clock-names = "gate",
// "sysclk_srcpll",
// "dclk_srcpll",
// "pdm_dclk",
// "pdm_sysclk";
pinctrl-names = "pdm_pins";
pinctrl-0 = <&pdmin>;
filter_mode = <1>; /* mode 0~4, defalut:1 */
@@ -999,10 +999,10 @@
audioresample: resample {
compatible = "amlogic, g12a-resample";
clocks = <&clkc CLKID_MPLL3
&clkaudio CLKID_AUDIO_MCLK_F
&clkaudio CLKID_AUDIO_RESAMPLE_CTRL>;
clock-names = "resample_pll", "resample_src", "resample_clk";
//clocks = <&clkc CLKID_MPLL3
// &clkaudio CLKID_AUDIO_MCLK_F
// &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>;
//clock-names = "resample_pll", "resample_src", "resample_clk";
/*same with toddr_src
* TDMIN_A, 0
* TDMIN_B, 1
arch/arm64/boot/dts/amlogic/mesong12b.dtsi
+214 -197
View File
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/amlogic,g12a-aoclkc.h>
#include <dt-bindings/clock/amlogic,g12a-clkc.h>
#include <dt-bindings/clock/amlogic,g12a-audio-clk.h>
#include <dt-bindings/iio/adc/amlogic-saradc.h>
@@ -57,12 +58,12 @@
enable-method = "psci";
//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
//sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
//clocks = <&clkc CLKID_CPU_CLK>,
// <&clkc CLKID_CPU_FCLK_P>,
// <&clkc CLKID_SYS1_PLL>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -75,12 +76,12 @@
reg = <0x0 0x1>;
enable-method = "psci";
//sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
//clocks = <&clkc CLKID_CPU_CLK>,
// <&clkc CLKID_CPU_FCLK_P>,
// <&clkc CLKID_SYS1_PLL>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -94,12 +95,12 @@
enable-method = "psci";
//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
//sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
clocks = <&clkc CLKID_CPUB_CLK>,
<&clkc CLKID_CPUB_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
//clocks = <&clkc CLKID_CPUB_CLK>,
// <&clkc CLKID_CPUB_FCLK_P>,
// <&clkc CLKID_SYS_PLL>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent";
operating-points-v2 = <&cpu_opp_table1>;
cpu-supply = <&vddcpu1>;
voltage-tolerance = <0>;
@@ -113,12 +114,12 @@
enable-method = "psci";
//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
//sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
clocks = <&clkc CLKID_CPUB_CLK>,
<&clkc CLKID_CPUB_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
//clocks = <&clkc CLKID_CPUB_CLK>,
// <&clkc CLKID_CPUB_FCLK_P>,
// <&clkc CLKID_SYS_PLL>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent";
operating-points-v2 = <&cpu_opp_table1>;
cpu-supply = <&vddcpu1>;
voltage-tolerance = <0>;
@@ -132,12 +133,12 @@
enable-method = "psci";
//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
//sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
clocks = <&clkc CLKID_CPUB_CLK>,
<&clkc CLKID_CPUB_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
//clocks = <&clkc CLKID_CPUB_CLK>,
// <&clkc CLKID_CPUB_FCLK_P>,
// <&clkc CLKID_SYS_PLL>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent";
operating-points-v2 = <&cpu_opp_table1>;
cpu-supply = <&vddcpu1>;
voltage-tolerance = <0>;
@@ -151,12 +152,12 @@
enable-method = "psci";
//cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
//sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>;
clocks = <&clkc CLKID_CPUB_CLK>,
<&clkc CLKID_CPUB_FCLK_P>,
<&clkc CLKID_SYS_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent";
//clocks = <&clkc CLKID_CPUB_CLK>,
// <&clkc CLKID_CPUB_FCLK_P>,
// <&clkc CLKID_SYS_PLL>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent";
operating-points-v2 = <&cpu_opp_table1>;
cpu-supply = <&vddcpu1>;
voltage-tolerance = <0>;
@@ -341,16 +342,16 @@
compatible = "amlogic, vpu-g12b";
dev_name = "vpu";
status = "disabled";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr_gate",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
//clocks = <&clkc CLKID_VAPB_MUX>,
// <&clkc CLKID_VPU_INTR>,
// <&clkc CLKID_VPU_P0_COMP>,
// <&clkc CLKID_VPU_P1_COMP>,
// <&clkc CLKID_VPU_MUX>;
//clock-names = "vapb_clk",
// "vpu_intr_gate",
// "vpu_clk0",
// "vpu_clk1",
// "vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
@@ -366,8 +367,8 @@
interrupts = <0 8 1>;
interrupt-names = "macirq";
status = "disabled";
clocks = <&clkc CLKID_ETH_CORE>;
clock-names = "ethclk81";
//clocks = <&clkc CLKID_ETH_CORE>;
//clock-names = "ethclk81";
pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
analog_val = <0x20200000 0x0000c000 0x00000023>;
};
@@ -426,8 +427,8 @@
usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_USB_GENERAL>;
clock-names = "dwc_general";
//clocks = <&clkc CLKID_USB_GENERAL>;
//clock-names = "dwc_general";
};
usb2_phy_v2: usb2phy@ffe09000 {
@@ -456,8 +457,8 @@
usb2-phy-reg = <0xffe09000>;
usb2-phy-reg-size = <0x80>;
interrupts = <0 16 4>;
clocks = <&clkc CLKID_PCIE_PLL>;
clock-names = "pcie_refpll";
//clocks = <&clkc CLKID_PCIE_PLL>;
//clock-names = "pcie_refpll";
};
dwc2_a: dwc2_a@ff400000 {
@@ -481,10 +482,10 @@
phy-reg-size = <0xa0>;
/** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
phy-interface = <0x0>;
clocks = <&clkc CLKID_USB_GENERAL
&clkc CLKID_USB1_TO_DDR>;
clock-names = "usb_general",
"usb1";
//clocks = <&clkc CLKID_USB_GENERAL
// &clkc CLKID_USB1_TO_DDR>;
//clock-names = "usb_general",
// "usb1";
};
wdt: watchdog@0xffd0f0d0 {
@@ -509,8 +510,8 @@
compatible = "amlogic,meson-g12a-saradc";
status = "disabled";
#io-channel-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>;
clock-names = "xtal", "saradc_clk";
//clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>;
//clock-names = "xtal", "saradc_clk";
interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xff809000 0x0 0x48>;
};
@@ -528,8 +529,8 @@
cal_d = <9411>;
rtemp = <115000>;
interrupts = <0 35 0>;
clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
clock-names = "ts_comp";
//clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
//clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
@@ -546,8 +547,8 @@
cal_d = <9411>;
rtemp = <115000>;
interrupts = <0 36 0>;
clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
clock-names = "ts_comp";
//clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
//clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
@@ -588,10 +589,9 @@
<64 65 66 67 68 69 70 71>;
};
meson_clk_msr {
compatible = "amlogic, gxl_measure";
reg = <0x0 0x18004 0x0 0x4
0x0 0x1800c 0x0 0x4>;
meson_clk_msr@18000 {
compatible = "amlogic,meson-g12b-clk-measure";
reg = <0x0 0x18000 0x0 0x1c>;
};
pwm_ab: pwm@1b000 {
@@ -650,8 +650,8 @@
<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c1: i2c@1e000 {
@@ -662,8 +662,8 @@
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c2: i2c@1d000 {
@@ -674,8 +674,8 @@
<GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c3: i2c@1c000 {
@@ -686,8 +686,8 @@
<GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
spicc0: spi@13000 {
@@ -695,9 +695,9 @@
"amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x44>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>,
<&clkc CLKID_SPICC0_COMP>;
clock-names = "core", "comp";
//clocks = <&clkc CLKID_SPICC0>,
// <&clkc CLKID_SPICC0_COMP>;
//clock-names = "core", "comp";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -708,9 +708,9 @@
"amlogic,meson-g12a-spicc";
reg = <0x0 0x15000 0x0 0x44>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>,
<&clkc CLKID_SPICC1_COMP>;
clock-names = "core", "comp";
//clocks = <&clkc CLKID_SPICC1>,
// <&clkc CLKID_SPICC1_COMP>;
//clock-names = "core", "comp";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -730,10 +730,19 @@
amlogic,has-chip-id;
};
meson_clk_msr@0 {
compatible = "amlogic,meson-g12a-clk-measure";
rti: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl",
"simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x320>;
status = "disabled";
clkc_AO: clock-controller {
compatible = "amlogic,meson-g12a-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
};
pwm_AO_ab: pwm@7000 {
@@ -773,8 +782,8 @@
<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c_AO_slave:i2c_slave@6000 {
@@ -839,11 +848,19 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
clkc: clock-controller@0 {
compatible = "amlogic,g12b-clkc-1";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3dc>;
hhi: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl",
"simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x400>;
clkc: clock-controller {
compatible = "amlogic,g12b-clkc";
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "xtal";
};
};
};/* end of hiubus*/
ion_dev {
@@ -923,10 +940,10 @@
reg = <0x0 0xffd24000 0x0 0x18>;
interrupts = <0 26 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART0>;
clock-names = "clk_uart",
"clk_gate";
//clocks = <&xtal
// &clkc CLKID_UART0>;
//clock-names = "clk_uart",
// "clk_gate";
fifosize = < 128 >;
pinctrl-names = "default";
pinctrl-0 = <&a_uart_pins>;
@@ -937,10 +954,10 @@
reg = <0x0 0xffd23000 0x0 0x18>;
interrupts = <0 75 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART1>;
clock-names = "clk_uart",
"clk_gate";
//clocks = <&xtal
// &clkc CLKID_UART1>;
//clock-names = "clk_uart",
// "clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&b_uart_pins>;
@@ -951,10 +968,10 @@
reg = <0x0 0xffd22000 0x0 0x18>;
interrupts = <0 93 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART1>;
clock-names = "clk_uart",
"clk_gate";
//clocks = <&xtal
// &clkc CLKID_UART1>;
//clock-names = "clk_uart",
// "clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&c_uart_pins>;
@@ -983,14 +1000,14 @@
num-lanes = <1>;
pcie-num = <1>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
"pcie_phy",
"pcie_hcsl";
//clocks = <&clkc CLKID_PCIE_PLL
// &clkc CLKID_PCIE_COMB
// &clkc CLKID_PCIE_PHY
// &clkc CLKID_PCIE_HCSL>;
//clock-names = "pcie_refpll",
// "pcie",
// "pcie_phy",
// "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
@@ -1007,16 +1024,16 @@
pinctrl-names="default", "hdmitx_i2c";
pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>;
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_MUX>;
clock-names = "venci_top_gate",
"venci_0_gate",
"venci_1_gate",
"hdmi_vapb_clk",
"hdmi_vpu_clk";
//clocks = <&clkc CLKID_VCLK2_ENCI
// &clkc CLKID_VCLK2_VENCI0
// &clkc CLKID_VCLK2_VENCI1
// &clkc CLKID_VAPB_MUX
// &clkc CLKID_VPU_MUX>;
//clock-names = "venci_top_gate",
// "venci_0_gate",
// "venci_1_gate",
// "hdmi_vapb_clk",
// "hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 4
0 3 1>;
@@ -1044,10 +1061,10 @@
compatible = "amlogic, galcore";
dev_name = "galcore";
status = "disabled";
clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
<&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
clock-names = "cts_vipnanoq_axi_clk_composite",
"cts_vipnanoq_core_clk_composite";
//clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
// <&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
//clock-names = "cts_vipnanoq_axi_clk_composite",
// "cts_vipnanoq_core_clk_composite";
interrupts = <0 147 4>;
interrupt-names = "galcore";
reg = <0x0 0xff100000 0x0 0x800
@@ -1141,10 +1158,10 @@
compatible = "amlogic, vout2";
dev_name = "vout";
status = "disabled";
clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>,
<&clkc CLKID_VPU_CLKC_MUX>;
clock-names = "vpu_clkc0",
"vpu_clkc";
//clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>,
// <&clkc CLKID_VPU_CLKC_MUX>;
//clock-names = "vpu_clkc0",
// "vpu_clkc";
fr_policy = <0>;
};
@@ -1152,22 +1169,22 @@
dummy_venc: dummy_venc {
compatible = "amlogic, dummy_venc";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCP
&clkc CLKID_VCLK2_VENCP0
&clkc CLKID_VCLK2_VENCP1
&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_VCLK2_ENCL
&clkc CLKID_VCLK2_VENCL>;
clock-names = "encp_top_gate",
"encp_int_gate0",
"encp_int_gate1",
"venci_top_gate",
"enci_int_gate0",
"enci_int_gate1",
"encl_top_gate",
"encl_int_gate";
//clocks = <&clkc CLKID_VCLK2_ENCP
// &clkc CLKID_VCLK2_VENCP0
// &clkc CLKID_VCLK2_VENCP1
// &clkc CLKID_VCLK2_ENCI
// &clkc CLKID_VCLK2_VENCI0
// &clkc CLKID_VCLK2_VENCI1
// &clkc CLKID_VCLK2_ENCL
// &clkc CLKID_VCLK2_VENCL>;
//clock-names = "encp_top_gate",
// "encp_int_gate0",
// "encp_int_gate1",
// "venci_top_gate",
// "enci_int_gate0",
// "enci_int_gate1",
// "encl_top_gate",
// "encl_int_gate";
};
vdac {
@@ -1188,12 +1205,12 @@
status = "disabled";
interrupts = <0 146 1>;
interrupt-names = "ge2d";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_G2D>,
<&clkc CLKID_GE2D_GATE>;
clock-names = "clk_vapb_0",
"clk_ge2d",
"clk_ge2d_gate";
//clocks = <&clkc CLKID_VAPB_MUX>,
// <&clkc CLKID_G2D>,
// <&clkc CLKID_GE2D_GATE>;
//clock-names = "clk_vapb_0",
// "clk_ge2d",
// "clk_ge2d_gate";
reg = <0x0 0xff940000 0x0 0x10000>;
};
@@ -1244,31 +1261,31 @@
0 0xFF63C100 0 0x0000004>;
interrupts = <0 144 1>;
interrupt-names = "GDC";
clocks = <&clkc CLKID_GDC_CORE_CLK_COMP
&clkc CLKID_GDC_AXI_CLK_COMP >;
clock-names = "core","axi";
//clocks = <&clkc CLKID_GDC_CORE_CLK_COMP
// &clkc CLKID_GDC_AXI_CLK_COMP >;
//clock-names = "core","axi";
};
mesonstream {
compatible = "amlogic, codec, streambuf";
dev_name = "mesonstream";
status = "disabled";
clocks = <&clkc CLKID_DOS_PARSER
&clkc CLKID_DEMUX
&clkc CLKID_AHB_ARB0
&clkc CLKID_DOS
&clkc CLKID_VDEC_MUX
&clkc CLKID_HCODEC_MUX
&clkc CLKID_HEVC_MUX
&clkc CLKID_HEVCF_MUX>;
clock-names = "parser_top",
"demux",
"ahbarb0",
"vdec",
"clk_vdec_mux",
"clk_hcodec_mux",
"clk_hevc_mux",
"clk_hevcb_mux";
//clocks = <&clkc CLKID_DOS_PARSER
// &clkc CLKID_DEMUX
// &clkc CLKID_AHB_ARB0
// &clkc CLKID_DOS
// &clkc CLKID_VDEC_MUX
// &clkc CLKID_HCODEC_MUX
// &clkc CLKID_HEVC_MUX
// &clkc CLKID_HEVCF_MUX>;
//clock-names = "parser_top",
// "demux",
// "ahbarb0",
// "vdec",
// "clk_vdec_mux",
// "clk_hcodec_mux",
// "clk_hevc_mux",
// "clk_hevcb_mux";
};
vdec {
@@ -1359,8 +1376,8 @@
/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
display_size_default = <1920 1080 1920 2160 32>;
/*1920*1080*4*3 = 0x17BB000*/
clocks = <&clkc CLKID_VPU_CLKC_MUX>;
clock-names = "vpu_clkc";
//clocks = <&clkc CLKID_VPU_CLKC_MUX>;
//clock-names = "vpu_clkc";
};
sd_emmc_c: emmc@ffe07000 {
@@ -1371,12 +1388,12 @@
pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
pinctrl-0 = <&emmc_clk_cmd_pins>;
pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV2P5>,
<&xtal>;
clock-names = "core","clkin0","clkin1","clkin2","xtal";
//clocks = <&clkc CLKID_SD_EMMC_C>,
// <&clkc CLKID_SD_EMMC_C_P0_COMP>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_FCLK_DIV2P5>,
// <&xtal>;
//clock-names = "core","clkin0","clkin1","clkin2","xtal";
bus-width = <8>;
cap-sd-highspeed;
@@ -1432,12 +1449,12 @@
pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>;
pinctrl-8 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>;
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV5>,
<&xtal>;
clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
//clocks = <&clkc CLKID_SD_EMMC_B>,
// <&clkc CLKID_SD_EMMC_B_P0_COMP>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_FCLK_DIV5>,
// <&xtal>;
//clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
bus-width = <4>;
cap-sd-highspeed;
@@ -1469,12 +1486,12 @@
pinctrl-0 = <&sdio_all_pins>;
pinctrl-1 = <&sdio_clk_cmd_pins>;
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV5>,
<&xtal>;
clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
//clocks = <&clkc CLKID_SD_EMMC_A>,
// <&clkc CLKID_SD_EMMC_A_P0_COMP>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_FCLK_DIV5>,
// <&xtal>;
//clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
bus-width = <4>;
cap-sd-highspeed;
@@ -1503,9 +1520,9 @@
pinctrl-0 = <&all_nand_pins>;
pinctrl-1 = <&all_nand_pins>;
pinctrl-2 = <&nand_cs_pins>;
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "gate", "fdiv2pll";
//clocks = <&clkc CLKID_SD_EMMC_C>,
// <&clkc CLKID_FCLK_DIV2>;
//clock-names = "gate", "fdiv2pll";
device_id = <0>;
/*fip/tpl configurations, must be same
@@ -1840,10 +1857,10 @@
interrupts = <0 142 4>;
interrupt-names = "ISP";
temper-buf-size = <24>;
clocks = <&clkc CLKID_MIPI_ISP_CLK_COMP>,
<&clkc CLKID_MIPI_CSI_PHY_CLK0_COMP>;
clock-names = "cts_mipi_isp_clk_composite",
"cts_mipi_csi_phy_clk0_composite";
//clocks = <&clkc CLKID_MIPI_ISP_CLK_COMP>,
// <&clkc CLKID_MIPI_CSI_PHY_CLK0_COMP>;
//clock-names = "cts_mipi_isp_clk_composite",
// "cts_mipi_csi_phy_clk0_composite";
link-device = <&isp_sc>;
};
@@ -1896,8 +1913,8 @@
write_cmd = <0x82000031>;
get_max_cmd = <0x82000033>;
key = <&efusekey>;
clocks = <&clkc CLKID_EFUSE>;
clock-names = "efuse_clk";
//clocks = <&clkc CLKID_EFUSE>;
//clock-names = "efuse_clk";
status = "disabled";
};
arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
+226 -212
View File
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/amlogic,g12a-aoclkc.h>
#include <dt-bindings/clock/amlogic,g12a-clkc.h>
#include <dt-bindings/clock/amlogic,sm1-audio-clk.h>
#include <dt-bindings/iio/adc/amlogic-saradc.h>
@@ -47,16 +48,16 @@
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
//clocks = <&clkc CLKID_CPU_CLK>,
// <&clkc CLKID_CPU_FCLK_P>,
// <&clkc CLKID_SYS_PLL>,
// <&clkc CLKID_DSU_CLK>,
// <&clkc CLKID_DSU_PRE_CLK>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent",
// "dsu_clk",
// "dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -69,16 +70,16 @@
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
//clocks = <&clkc CLKID_CPU_CLK>,
// <&clkc CLKID_CPU_FCLK_P>,
// <&clkc CLKID_SYS_PLL>,
// <&clkc CLKID_DSU_CLK>,
// <&clkc CLKID_DSU_PRE_CLK>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent",
// "dsu_clk",
// "dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -91,16 +92,16 @@
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
//clocks = <&clkc CLKID_CPU_CLK>,
// <&clkc CLKID_CPU_FCLK_P>,
// <&clkc CLKID_SYS_PLL>,
// <&clkc CLKID_DSU_CLK>,
// <&clkc CLKID_DSU_PRE_CLK>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent",
// "dsu_clk",
// "dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -113,16 +114,16 @@
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_FCLK_P>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_PRE_CLK>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent";
//clocks = <&clkc CLKID_CPU_CLK>,
// <&clkc CLKID_CPU_FCLK_P>,
// <&clkc CLKID_SYS_PLL>,
// <&clkc CLKID_DSU_CLK>,
// <&clkc CLKID_DSU_PRE_CLK>;
//clock-names = "core_clk",
// "low_freq_clk_parent",
// "high_freq_clk_parent",
// "dsu_clk",
// "dsu_pre_parent";
operating-points-v2 = <&cpu_opp_table0>;
cpu-supply = <&vddcpu0>;
voltage-tolerance = <0>;
@@ -308,16 +309,16 @@
compatible = "amlogic, vpu-sm1";
dev_name = "vpu";
status = "disabled";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_VPU_INTR>,
<&clkc CLKID_VPU_P0_COMP>,
<&clkc CLKID_VPU_P1_COMP>,
<&clkc CLKID_VPU_MUX>;
clock-names = "vapb_clk",
"vpu_intr_gate",
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
//clocks = <&clkc CLKID_VAPB_MUX>,
// <&clkc CLKID_VPU_INTR>,
// <&clkc CLKID_VPU_P0_COMP>,
// <&clkc CLKID_VPU_P1_COMP>,
// <&clkc CLKID_VPU_MUX>;
//clock-names = "vapb_clk",
// "vpu_intr_gate",
// "vpu_clk0",
// "vpu_clk1",
// "vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
@@ -333,8 +334,8 @@
interrupts = <0 8 1>;
interrupt-names = "macirq";
status = "disabled";
clocks = <&clkc CLKID_ETH_CORE>;
clock-names = "ethclk81";
//clocks = <&clkc CLKID_ETH_CORE>;
//clock-names = "ethclk81";
pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
analog_val = <0x20200000 0x0000c000 0x00000023>;
};
@@ -393,8 +394,8 @@
usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_USB_GENERAL>;
clock-names = "dwc_general";
//clocks = <&clkc CLKID_USB_GENERAL>;
//clock-names = "dwc_general";
};
usb2_phy_v2: usb2phy@ffe09000 {
@@ -426,8 +427,8 @@
usb2-phy-reg = <0xffe09000>;
usb2-phy-reg-size = <0x80>;
interrupts = <0 16 4>;
clocks = <&clkc CLKID_PCIE_PLL>;
clock-names = "pcie_refpll";
//clocks = <&clkc CLKID_PCIE_PLL>;
//clock-names = "pcie_refpll";
pwr-ctl = <1>;
};
@@ -452,10 +453,10 @@
phy-reg-size = <0xa0>;
/** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
phy-interface = <0x2>;
clocks = <&clkc CLKID_USB_GENERAL
&clkc CLKID_USB1_TO_DDR>;
clock-names = "usb_general",
"usb1";
//clocks = <&clkc CLKID_USB_GENERAL
// &clkc CLKID_USB1_TO_DDR>;
//clock-names = "usb_general",
// "usb1";
};
wdt: watchdog@0xffd0f0d0 {
@@ -488,8 +489,8 @@
compatible = "amlogic,meson-g12a-saradc";
status = "disabled";
#io-channel-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>;
clock-names = "xtal", "saradc_clk";
//clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>;
//clock-names = "xtal", "saradc_clk";
interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xff809000 0x0 0x48>;
};
@@ -539,11 +540,9 @@
<64 65 66 67 68 69 70 71>;
};
meson_clk_msr {
compatible = "amlogic, sm1-measure";
reg = <0x0 0x18004 0x0 0x4
0x0 0x1800c 0x0 0x4>;
ringctrl = <0xff6345fc>;
meson_clk_msr@18000 {
compatible = "amlogic,meson-sm1-clk-measure";
reg = <0x0 0x18000 0x0 0x1c>;
};
pwm_ab: pwm@1b000 {
@@ -602,8 +601,8 @@
<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c1: i2c@1e000 {
@@ -614,8 +613,8 @@
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c2: i2c@1d000 {
@@ -626,8 +625,8 @@
<GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c3: i2c@1c000 {
@@ -638,17 +637,17 @@
<GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
spicc0: spi@13000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x44>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>,
<&clkc CLKID_SPICC0_COMP>;
clock-names = "core", "comp";
//clocks = <&clkc CLKID_SPICC0>,
// <&clkc CLKID_SPICC0_COMP>;
//clock-names = "core", "comp";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -658,9 +657,9 @@
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x15000 0x0 0x44>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>,
<&clkc CLKID_SPICC1_COMP>;
clock-names = "core", "comp";
//clocks = <&clkc CLKID_SPICC1>,
// <&clkc CLKID_SPICC1_COMP>;
//clock-names = "core", "comp";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -680,11 +679,19 @@
amlogic,has-chip-id;
};
aoclkc: clock-controller@0 {
compatible = "amlogic,sm1-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0x0 0x0 0x0 0x3dc>;
rti: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl",
"simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x320>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-g12a-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
};
pwm_AO_ab: pwm@7000 {
@@ -725,8 +732,8 @@
<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_I2C>;
clock-names = "clk_i2c";
//clocks = <&clkc CLKID_I2C>;
//clock-names = "clk_i2c";
};
i2c_AO_slave:i2c_slave@6000 {
@@ -782,10 +789,17 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
clkc: clock-controller@0 {
compatible = "amlogic,sm1-clkc-1";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3dc>;
hhi: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl",
"simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x400>;
clkc: clock-controller {
compatible = "amlogic,sm1-clkc";
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "xtal";
};
};
// clkc_b: clock-controller@1 {
@@ -861,20 +875,20 @@
"rx_dmac",
"rx_top";
clocks = < &clkaudio CLKID_EARCRX_CMDC
&clkaudio CLKID_EARCRX_DMAC
&clkc CLKID_FCLK_DIV4
&clkc CLKID_FCLK_DIV4
&clkaudio CLKID_EARCTX_CMDC
&clkaudio CLKID_EARCTX_DMAC
&clkc CLKID_FCLK_DIV4
&clkc CLKID_MPLL1
>;
clock-names =
"rx_cmdc",
"rx_dmac",
"rx_cmdc_srcpll",
"rx_dmac_srcpll";
//clocks = < &clkaudio CLKID_EARCRX_CMDC
// &clkaudio CLKID_EARCRX_DMAC
// &clkc CLKID_FCLK_DIV4
// &clkc CLKID_FCLK_DIV4
// &clkaudio CLKID_EARCTX_CMDC
// &clkaudio CLKID_EARCTX_DMAC
// &clkc CLKID_FCLK_DIV4
// &clkc CLKID_MPLL1
// >;
//clock-names =
// "rx_cmdc",
// "rx_dmac",
// "rx_cmdc_srcpll",
// "rx_dmac_srcpll";
interrupts = <
GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
@@ -932,10 +946,10 @@
reg = <0x0 0xffd24000 0x0 0x18>;
interrupts = <0 26 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART0>;
clock-names = "clk_uart",
"clk_gate";
//clocks = <&xtal
// &clkc CLKID_UART0>;
//clock-names = "clk_uart",
// "clk_gate";
fifosize = < 128 >;
pinctrl-names = "default";
pinctrl-0 = <&a_uart_pins>;
@@ -946,10 +960,10 @@
reg = <0x0 0xffd23000 0x0 0x18>;
interrupts = <0 75 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART1>;
clock-names = "clk_uart",
"clk_gate";
//clocks = <&xtal
// &clkc CLKID_UART1>;
//clock-names = "clk_uart",
// "clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&b_uart_pins>;
@@ -960,10 +974,10 @@
reg = <0x0 0xffd22000 0x0 0x18>;
interrupts = <0 93 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_UART1>;
clock-names = "clk_uart",
"clk_gate";
//clocks = <&xtal
// &clkc CLKID_UART1>;
//clock-names = "clk_uart",
// "clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&c_uart_pins>;
@@ -992,14 +1006,14 @@
num-lanes = <1>;
pcie-num = <1>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_PCIE_COMB
&clkc CLKID_PCIE_PHY
&clkc CLKID_PCIE_HCSL>;
clock-names = "pcie_refpll",
"pcie",
"pcie_phy",
"pcie_hcsl";
//clocks = <&clkc CLKID_PCIE_PLL
// &clkc CLKID_PCIE_COMB
// &clkc CLKID_PCIE_PHY
// &clkc CLKID_PCIE_HCSL>;
//clock-names = "pcie_refpll",
// "pcie",
// "pcie_phy",
// "pcie_hcsl";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-apb-rst-bit = <15>;
@@ -1017,16 +1031,16 @@
pinctrl-names="default", "hdmitx_i2c";
pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>;
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_VAPB_MUX
&clkc CLKID_VPU_MUX>;
clock-names = "venci_top_gate",
"venci_0_gate",
"venci_1_gate",
"hdmi_vapb_clk",
"hdmi_vpu_clk";
//clocks = <&clkc CLKID_VCLK2_ENCI
// &clkc CLKID_VCLK2_VENCI0
// &clkc CLKID_VCLK2_VENCI1
// &clkc CLKID_VAPB_MUX
// &clkc CLKID_VPU_MUX>;
//clock-names = "venci_top_gate",
// "venci_0_gate",
// "venci_1_gate",
// "hdmi_vapb_clk",
// "hdmi_vpu_clk";
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 4
0 3 1>;
@@ -1048,10 +1062,10 @@
compatible = "amlogic, galcore";
dev_name = "galcore";
status = "disabled";
clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
<&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
clock-names = "cts_vipnanoq_axi_clk_composite",
"cts_vipnanoq_core_clk_composite";
//clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>,
// <&clkc CLKID_VNANOQ_CORE_CLK_COMP>;
//clock-names = "cts_vipnanoq_axi_clk_composite",
// "cts_vipnanoq_core_clk_composite";
interrupts = <0 186 4>;
interrupt-names = "galcore";
reg = <0x0 0xff100000 0x0 0x800
@@ -1145,10 +1159,10 @@
compatible = "amlogic, vout2";
dev_name = "vout";
status = "disabled";
clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>,
<&clkc CLKID_VPU_CLKC_MUX>;
clock-names = "vpu_clkc0",
"vpu_clkc";
//clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>,
// <&clkc CLKID_VPU_CLKC_MUX>;
//clock-names = "vpu_clkc0",
// "vpu_clkc";
fr_policy = <0>;
};
@@ -1156,22 +1170,22 @@
dummy_venc: dummy_venc {
compatible = "amlogic, dummy_venc";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCP
&clkc CLKID_VCLK2_VENCP0
&clkc CLKID_VCLK2_VENCP1
&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_VCLK2_ENCL
&clkc CLKID_VCLK2_VENCL>;
clock-names = "encp_top_gate",
"encp_int_gate0",
"encp_int_gate1",
"venci_top_gate",
"enci_int_gate0",
"enci_int_gate1",
"encl_top_gate",
"encl_int_gate";
//clocks = <&clkc CLKID_VCLK2_ENCP
// &clkc CLKID_VCLK2_VENCP0
// &clkc CLKID_VCLK2_VENCP1
// &clkc CLKID_VCLK2_ENCI
// &clkc CLKID_VCLK2_VENCI0
// &clkc CLKID_VCLK2_VENCI1
// &clkc CLKID_VCLK2_ENCL
// &clkc CLKID_VCLK2_VENCL>;
//clock-names = "encp_top_gate",
// "encp_int_gate0",
// "encp_int_gate1",
// "venci_top_gate",
// "enci_int_gate0",
// "enci_int_gate1",
// "encl_top_gate",
// "encl_int_gate";
};
vdac {
@@ -1192,12 +1206,12 @@
status = "disabled";
interrupts = <0 146 1>;
interrupt-names = "ge2d";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_G2D>,
<&clkc CLKID_GE2D_GATE>;
clock-names = "clk_vapb_0",
"clk_ge2d",
"clk_ge2d_gate";
//clocks = <&clkc CLKID_VAPB_MUX>,
// <&clkc CLKID_G2D>,
// <&clkc CLKID_GE2D_GATE>;
//clock-names = "clk_vapb_0",
// "clk_ge2d",
// "clk_ge2d_gate";
reg = <0x0 0xff940000 0x0 0x10000>;
};
@@ -1242,24 +1256,24 @@
compatible = "amlogic, codec, streambuf";
dev_name = "mesonstream";
status = "disabled";
clocks = <&clkc CLKID_DOS_PARSER
&clkc CLKID_DEMUX
&clkc CLKID_AHB_ARB0
&clkc CLKID_DOS
&clkc CLKID_CLK81
&clkc CLKID_VDEC_MUX
&clkc CLKID_HCODEC_MUX
&clkc CLKID_HEVC_MUX
&clkc CLKID_HEVCF_MUX>;
clock-names = "parser_top",
"demux",
"ahbarb0",
"vdec",
"clk_81",
"clk_vdec_mux",
"clk_hcodec_mux",
"clk_hevc_mux",
"clk_hevcb_mux";
//clocks = <&clkc CLKID_DOS_PARSER
// &clkc CLKID_DEMUX
// &clkc CLKID_AHB_ARB0
// &clkc CLKID_DOS
// &clkc CLKID_CLK81
// &clkc CLKID_VDEC_MUX
// &clkc CLKID_HCODEC_MUX
// &clkc CLKID_HEVC_MUX
// &clkc CLKID_HEVCF_MUX>;
//clock-names = "parser_top",
// "demux",
// "ahbarb0",
// "vdec",
// "clk_81",
// "clk_vdec_mux",
// "clk_hcodec_mux",
// "clk_hevc_mux",
// "clk_hevcb_mux";
};
vdec {
@@ -1334,8 +1348,8 @@
/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
display_size_default = <1920 1080 1920 2160 32>;
/*1920*1080*4*3 = 0x17BB000*/
clocks = <&clkc CLKID_VPU_CLKC_MUX>;
clock-names = "vpu_clkc";
//clocks = <&clkc CLKID_VPU_CLKC_MUX>;
//clock-names = "vpu_clkc";
};
irblaster: meson-irblaster {
compatible = "amlogic, meson_irblaster";
@@ -1355,12 +1369,12 @@
pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
pinctrl-0 = <&emmc_clk_cmd_pins>;
pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV2P5>,
<&xtal>;
clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
//clocks = <&clkc CLKID_SD_EMMC_C>,
// <&clkc CLKID_SD_EMMC_C_P0_COMP>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_FCLK_DIV2P5>,
// <&xtal>;
//clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
bus-width = <8>;
cap-sd-highspeed;
@@ -1422,12 +1436,12 @@
&ao_to_sd_uart_pins>;
pinctrl-9 = <&sd_all_pd_pins>;
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV5>,
<&xtal>;
clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
//clocks = <&clkc CLKID_SD_EMMC_B>,
// <&clkc CLKID_SD_EMMC_B_P0_COMP>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_FCLK_DIV5>,
// <&xtal>;
//clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
bus-width = <4>;
cap-sd-highspeed;
@@ -1459,12 +1473,12 @@
pinctrl-0 = <&sdio_all_pins>;
pinctrl-1 = <&sdio_clk_cmd_pins>;
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_P0_COMP>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_FCLK_DIV5>,
<&xtal>;
clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
//clocks = <&clkc CLKID_SD_EMMC_A>,
// <&clkc CLKID_SD_EMMC_A_P0_COMP>,
// <&clkc CLKID_FCLK_DIV2>,
// <&clkc CLKID_FCLK_DIV5>,
// <&xtal>;
//clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
bus-width = <4>;
cap-sd-highspeed;
@@ -1493,8 +1507,8 @@
pinctrl-1 = <&all_nand_pins>;
pinctrl-2 = <&nand_cs_pins>;
device_id = <0>;
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_FCLK_DIV2>;
//clocks = <&clkc CLKID_SD_EMMC_C>,
// <&clkc CLKID_FCLK_DIV2>;
clock-names = "gate", "fdiv2pll";
bl_mode = <1>;
fip_copies = <4>;
@@ -1614,8 +1628,8 @@
write_cmd = <0x82000031>;
get_max_cmd = <0x82000033>;
key = <&efusekey>;
clocks = <&clkc CLKID_EFUSE>;
clock-names = "efuse_clk";
//clocks = <&clkc CLKID_EFUSE>;
//clock-names = "efuse_clk";
status = "disabled";
};
@@ -1636,8 +1650,8 @@
cal_d = <9411>;
rtemp = <115000>;
interrupts = <0 35 0>;
clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
clock-names = "ts_comp";
//clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
//clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
@@ -1654,8 +1668,8 @@
cal_d = <9411>;
rtemp = <115000>;
interrupts = <0 36 0>;
clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
clock-names = "ts_comp";
//clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/
//clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
+113 -113
View File
@@ -158,14 +158,14 @@
compatible = "amlogic, cvbsout-sm1";
dev_name = "cvbsout";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
&clkc CLKID_DAC_CLK>;
clock-names = "venci_top_gate",
"venci_0_gate",
"venci_1_gate",
"vdac_clk_gate";
//clocks = <&clkc CLKID_VCLK2_ENCI
// &clkc CLKID_VCLK2_VENCI0
// &clkc CLKID_VCLK2_VENCI1
// &clkc CLKID_DAC_CLK>;
//clock-names = "venci_top_gate",
// "venci_0_gate",
// "venci_1_gate",
// "vdac_clk_gate";
/* clk path */
/* 0:vid_pll vid2_clk */
/* 1:gp0_pll vid2_clk */
@@ -268,10 +268,10 @@
interrupts = <0 46 1
0 40 1>;
interrupt-names = "pre_irq", "post_irq";
clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
<&clkc CLKID_VPU_CLKB_COMP>;
clock-names = "vpu_clkb_tmp_composite",
"vpu_clkb_composite";
//clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>,
// <&clkc CLKID_VPU_CLKB_COMP>;
//clock-names = "vpu_clkb_tmp_composite",
// "vpu_clkb_composite";
clock-range = <334 667>;
/* buffer-size = <3621952>;(yuv422 8bit) */
buffer-size = <4074560>;/*yuv422 fullpack*/
@@ -302,10 +302,10 @@
dev_name = "amvdec_656in";
status = "disabled";
reg = <0x0 0xffe02000 0x0 0x7c>;
clocks = <&clkc CLKID_BT656_COMP>,
<&clkc CLKID_BT656>;
clock-names = "cts_bt656_clk1",
"clk_gate_bt656";
//clocks = <&clkc CLKID_BT656_COMP>,
// <&clkc CLKID_BT656>;
//clock-names = "cts_bt656_clk1",
// "clk_gate_bt656";
/* bt656in1, bt656in2 */
bt656in1 {
bt656_id = <1>;
@@ -318,8 +318,8 @@
status = "disabled";
pinctrl-names="default";
pinctrl-0=<&gen_clk_ee_z>;
clocks = <&clkc CLKID_GEN_CLK>;
clock-names = "g12a_24m";
//clocks = <&clkc CLKID_GEN_CLK>;
//clock-names = "g12a_24m";
cam_0{
cam_name = "ov5640";
front_back = <0>;
@@ -346,10 +346,10 @@
<0x0 0xffe0c000 0x0 0x00000100>,
<0x0 0xffe0d000 0x0 0x00000100>;
reg-names = "csi_phy", "csi_host", "csi_adapt";
clocks = <&clkc CLKID_CSI_ADAPT_CLK_COMP>,
<&clkc CLKID_MIPI_CSI_PHY_CLK_COMP>;
clock-names = "cts_csi_adapt_clk_composite",
"cts_csi_phy_clk_composite";
//clocks = <&clkc CLKID_CSI_ADAPT_CLK_COMP>,
// <&clkc CLKID_MIPI_CSI_PHY_CLK_COMP>;
//clock-names = "cts_csi_adapt_clk_composite",
// "cts_csi_phy_clk_composite";
interrupts = <0 1 0>;
interrupt-names = "csi_phy";
};
@@ -731,14 +731,14 @@
};
audiolocker: locker {
compatible = "amlogic, audiolocker";
clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT
&clkaudio CLKID_AUDIO_LOCKER_IN
&clkaudio CLKID_AUDIO_MCLK_D
&clkaudio CLKID_AUDIO_MCLK_E
&clkc CLKID_MPLL1
&clkc CLKID_MPLL2>;
clock-names = "lock_out", "lock_in", "out_src",
"in_src", "out_calc", "in_ref";
//clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT
// &clkaudio CLKID_AUDIO_LOCKER_IN
// &clkaudio CLKID_AUDIO_MCLK_D
// &clkaudio CLKID_AUDIO_MCLK_E
// &clkc CLKID_MPLL1
// &clkc CLKID_MPLL2>;
//clock-names = "lock_out", "lock_in", "out_src",
// "in_src", "out_calc", "in_ref";
interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "irq";
frequency = <49000000>; /* pll */
@@ -770,10 +770,10 @@
"dvr1_irq",
"dvrfill0_fill",
"dvrfill1_flush";
clocks = <&clkc CLKID_DEMUX
&clkc CLKID_AHB_ARB0
&clkc CLKID_DOS_PARSER>;
clock-names = "demux", "ahbarb0", "uparsertop";
//clocks = <&clkc CLKID_DEMUX
// &clkc CLKID_AHB_ARB0
// &clkc CLKID_DOS_PARSER>;
//clock-names = "demux", "ahbarb0", "uparsertop";
};
cpu_opp_table0: cpu_opp_table0 {
@@ -1132,9 +1132,9 @@
dai-tdm-lane-slot-mask-in = <0 1>;
dai-tdm-oe-lane-slot-mask-out = <1 0>;
dai-tdm-clk-sel = <0>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_A
&clkc CLKID_MPLL0>;
clock-names = "mclk", "clk_srcpll";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_A
// &clkc CLKID_MPLL0>;
//clock-names = "mclk", "clk_srcpll";
pinctrl-names = "tdm_pins";
pinctrl-0 = <&tdmout_a &tdmin_a>;
@@ -1147,13 +1147,13 @@
dai-tdm-lane-slot-mask-in = <0 1 0 0>;
dai-tdm-lane-slot-mask-out = <1 0 0 0>;
dai-tdm-clk-sel = <1>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_B
&clkaudio CLKID_AUDIO_MCLK_PAD0
&clkc CLKID_MPLL1
&clkc CLKID_MPLL0
&clkaudio CLKID_AUDIO_SPDIFOUT_A>;
clock-names = "mclk", "mclk_pad", "clk_srcpll",
"samesource_srcpll", "samesource_clk";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_B
// &clkaudio CLKID_AUDIO_MCLK_PAD0
// &clkc CLKID_MPLL1
// &clkc CLKID_MPLL0
// &clkaudio CLKID_AUDIO_SPDIFOUT_A>;
//clock-names = "mclk", "mclk_pad", "clk_srcpll",
// "samesource_srcpll", "samesource_clk";
pinctrl-names = "tdm_pins";
pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>;
/*
@@ -1183,9 +1183,9 @@
#dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>;
dai-tdm-clk-sel = <2>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_C
&clkc CLKID_MPLL2>;
clock-names = "mclk", "clk_srcpll";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_C
// &clkc CLKID_MPLL2>;
//clock-names = "mclk", "clk_srcpll";
pinctrl-names = "tdm_pins";
pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>;
@@ -1199,9 +1199,9 @@
dai-tdm-lane-lb-slot-mask-in = <1 0 0 0>;
dai-tdm-clk-sel = <1>;
clocks = <&clkaudio CLKID_AUDIO_MCLK_B
&clkc CLKID_MPLL1>;
clock-names = "mclk", "clk_srcpll";
//clocks = <&clkaudio CLKID_AUDIO_MCLK_B
// &clkc CLKID_MPLL1>;
//clock-names = "mclk", "clk_srcpll";
/*
* select tdmin_lb src;
@@ -1244,14 +1244,14 @@
spdifa: spdif@0 {
compatible = "amlogic, sm1-snd-spdif-a";
#sound-dai-cells = <0>;
clocks = <&clkc CLKID_MPLL0
&clkc CLKID_FCLK_DIV4
&clkaudio CLKID_AUDIO_GATE_SPDIFIN
&clkaudio CLKID_AUDIO_GATE_SPDIFOUT_A
&clkaudio CLKID_AUDIO_SPDIFIN
&clkaudio CLKID_AUDIO_SPDIFOUT_A>;
clock-names = "sysclk", "fixed_clk", "gate_spdifin",
"gate_spdifout", "clk_spdifin", "clk_spdifout";
//clocks = <&clkc CLKID_MPLL0
// &clkc CLKID_FCLK_DIV4
// &clkaudio CLKID_AUDIO_GATE_SPDIFIN
// &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_A
// &clkaudio CLKID_AUDIO_SPDIFIN
// &clkaudio CLKID_AUDIO_SPDIFOUT_A>;
//clock-names = "sysclk", "fixed_clk", "gate_spdifin",
// "gate_spdifout", "clk_spdifin", "clk_spdifout";
interrupts =
<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
@@ -1267,11 +1267,11 @@
spdifb: spdif@1 {
compatible = "amlogic, sm1-snd-spdif-b";
#sound-dai-cells = <0>;
clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
&clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B
&clkaudio CLKID_AUDIO_SPDIFOUT_B>;
clock-names = "sysclk",
"gate_spdifout", "clk_spdifout";
//clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/
// &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B
// &clkaudio CLKID_AUDIO_SPDIFOUT_B>;
//clock-names = "sysclk",
// "gate_spdifout", "clk_spdifout";
status = "disabled";
};
@@ -1279,16 +1279,16 @@
compatible = "amlogic, sm1-snd-pdm";
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1>;
clock-names = "gate",
"sysclk_srcpll",
"dclk_srcpll",
"pdm_dclk",
"pdm_sysclk";
//clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
// &clkc CLKID_HIFI_PLL
// &clkc CLKID_HIFI_PLL
// &clkaudio CLKID_AUDIO_PDMIN0
// &clkaudio CLKID_AUDIO_PDMIN1>;
//clock-names = "gate",
// "sysclk_srcpll",
// "dclk_srcpll",
// "pdm_dclk",
// "pdm_sysclk";
pinctrl-names = "pdm_pins";
pinctrl-0 = <&pdmin>;
@@ -1301,10 +1301,10 @@
asrca: resample@0 {
compatible = "amlogic, sm1-resample";
clocks = <&clkc CLKID_MPLL3
&clkaudio CLKID_AUDIO_MCLK_F
&clkaudio CLKID_AUDIO_RESAMPLE_A>;
clock-names = "resample_pll", "resample_src", "resample_clk";
//clocks = <&clkc CLKID_MPLL3
// &clkaudio CLKID_AUDIO_MCLK_F
// &clkaudio CLKID_AUDIO_RESAMPLE_A>;
//clock-names = "resample_pll", "resample_src", "resample_clk";
/*same with toddr_src
* TDMIN_A, 0
* TDMIN_B, 1
@@ -1323,10 +1323,10 @@
compatible = "amlogic, snd-vad";
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_VAD>;
clock-names = "gate", "pll", "clk";
//clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD
// &clkc CLKID_HIFI_PLL
// &clkaudio CLKID_AUDIO_VAD>;
//clock-names = "gate", "pll", "clk";
interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING
GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
@@ -1359,20 +1359,20 @@
compatible = "amlogic, sm1-loopbacka";
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_HIFI_PLL
&clkc CLKID_HIFI_PLL
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
&clkaudio CLKID_AUDIO_MCLK_A>;
clock-names = "pdm_gate",
"pdm_sysclk_srcpll",
"pdm_dclk_srcpll",
"pdm_dclk",
"pdm_sysclk",
"tdminlb_mpll",
"tdminlb_mclk";
//clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
// &clkc CLKID_HIFI_PLL
// &clkc CLKID_HIFI_PLL
// &clkaudio CLKID_AUDIO_PDMIN0
// &clkaudio CLKID_AUDIO_PDMIN1
// &clkc CLKID_MPLL0
// &clkaudio CLKID_AUDIO_MCLK_A>;
//clock-names = "pdm_gate",
// "pdm_sysclk_srcpll",
// "pdm_dclk_srcpll",
// "pdm_dclk",
// "pdm_sysclk",
// "tdminlb_mpll",
// "tdminlb_mclk";
/* datain src
* 0: tdmin_a;
@@ -1414,20 +1414,20 @@
compatible = "amlogic, sm1-loopbackb";
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
&clkc CLKID_FCLK_DIV3
&clkc CLKID_MPLL3
&clkaudio CLKID_AUDIO_PDMIN0
&clkaudio CLKID_AUDIO_PDMIN1
&clkc CLKID_MPLL0
&clkaudio CLKID_AUDIO_MCLK_A>;
clock-names = "pdm_gate",
"pdm_sysclk_srcpll",
"pdm_dclk_srcpll",
"pdm_dclk",
"pdm_sysclk",
"tdminlb_mpll",
"tdminlb_mclk";
//clocks = <&clkaudio CLKID_AUDIO_GATE_PDM
// &clkc CLKID_FCLK_DIV3
// &clkc CLKID_MPLL3
// &clkaudio CLKID_AUDIO_PDMIN0
// &clkaudio CLKID_AUDIO_PDMIN1
// &clkc CLKID_MPLL0
// &clkaudio CLKID_AUDIO_MCLK_A>;
//clock-names = "pdm_gate",
// "pdm_sysclk_srcpll",
// "pdm_dclk_srcpll",
// "pdm_dclk",
// "pdm_sysclk",
// "tdminlb_mpll",
// "tdminlb_mclk";
/* calc mclk for datain_lb */
mclk-fs = <256>;
@@ -1467,10 +1467,10 @@
aed:effect {
compatible = "amlogic, snd-effect-v3";
#sound-dai-cells = <0>;
clocks = <&clkaudio CLKID_AUDIO_GATE_EQDRC
&clkc CLKID_FCLK_DIV5
&clkaudio CLKID_AUDIO_EQDRC>;
clock-names = "gate", "srcpll", "eqdrc";
//clocks = <&clkaudio CLKID_AUDIO_GATE_EQDRC
// &clkc CLKID_FCLK_DIV5
// &clkaudio CLKID_AUDIO_EQDRC>;
//clock-names = "gate", "srcpll", "eqdrc";
/*
* 0:tdmout_a
* 1:tdmout_b
arch/arm64/configs/meson64_a64_smarthome_defconfig
+1
View File
@@ -366,6 +366,7 @@ CONFIG_AMLOGIC_CLK_DEBUG=y
CONFIG_AMLOGIC_COMMON_CLK_C2=m
CONFIG_AMLOGIC_COMMON_CLK_C3=m
CONFIG_AMLOGIC_COMMON_CLK_A1=m
CONFIG_AMLOGIC_COMMON_CLK_G12A=m
CONFIG_AMLOGIC_SECMON=m
CONFIG_AMLOGIC_DOLBY_FW=y
CONFIG_AMLOGIC_MEDIA_MODULE=m
drivers/clk/meson/Kconfig
+18
View File
@@ -167,4 +167,22 @@ config AMLOGIC_COMMON_CLK_T5M
help
Support for the clock controller on Amlogic T5M
devices, aka t5m. Say Y if you want peripherals to work.
config AMLOGIC_COMMON_CLK_G12A
tristate "G12 and SM1 SoC clock controllers support"
depends on ARM64
default y
select AMLOGIC_COMMON_CLK_MESON_REGMAP
select AMLOGIC_COMMON_CLK_MESON_DUALDIV
select AMLOGIC_COMMON_CLK_MESON_MPLL
select AMLOGIC_COMMON_CLK_MESON_PLL
select AMLOGIC_COMMON_CLK_MESON_AO_CLKC
select AMLOGIC_COMMON_CLK_MESON_EE_CLKC
select AMLOGIC_COMMON_CLK_MESON_CPU_DYNDIV
select AMLOGIC_COMMON_CLK_MESON_VID_PLL_DIV
select MFD_SYSCON
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
endmenu
drivers/clk/meson/Makefile
+15
View File
@@ -88,3 +88,18 @@ $(T5M_MODULE_NAME)-y += t5m.o
PR_FMT_T5M = $(subst amlogic-,,$(T5M_MODULE_NAME))
PR_FMT_DEFINE_T5M="-Dpr_fmt(fmt)= \"[$(PR_FMT_T5M)]: \" fmt"
CFLAGS_t5m.o += $(PR_FMT_DEFINE_T5M)
G12A_MODULE_NAME = amlogic-clk-soc-g12a
obj-$(CONFIG_AMLOGIC_COMMON_CLK_G12A) += $(G12A_MODULE_NAME).o
$(G12A_MODULE_NAME)-y += g12a.o
PR_FMT_G12A = $(subst amlogic-,,$(G12A_MODULE_NAME))
PR_FMT_DEFINE_G12A="-Dpr_fmt(fmt)= \"[$(PR_FMT_G12A)]: \" fmt"
CFLAGS_g12a.o += $(PR_FMT_DEFINE_G12A)
G12A_AO_MODULE_NAME = amlogic-aoclk-g12a
obj-$(CONFIG_AMLOGIC_COMMON_CLK_G12A) += $(G12A_AO_MODULE_NAME).o
$(G12A_AO_MODULE_NAME)-y += g12a-aoclk.o
PR_FMT_G12A_AO = $(subst amlogic-,,$(G12A_AO_MODULE_NAME))
PR_FMT_DEFINE_G12A_AO="-Dpr_fmt(fmt)= \"[$(PR_FMT_G12A_AO)]: \" fmt"
CFLAGS_g12a_ao.o += $(PR_FMT_DEFINE_G12A_AO)
drivers/clk/meson/g12a-aoclk.c
+471
View File
@@ -0,0 +1,471 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
#include "g12a-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
/*
* AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4.
*/
#define AO_RTI_STATUS_REG3 0x0C
#define AO_RTI_PWR_CNTL_REG0 0x10
#define AO_RTI_GEN_CNTL_REG0 0x40
#define AO_CLK_GATE0 0x4c
#define AO_CLK_GATE0_SP 0x50
#define AO_OSCIN_CNTL 0x58
#define AO_CEC_CLK_CNTL_REG0 0x74
#define AO_CEC_CLK_CNTL_REG1 0x78
#define AO_SAR_CLK 0x90
#define AO_RTC_ALT_CLK_CNTL0 0x94
#define AO_RTC_ALT_CLK_CNTL1 0x98
/*
* Like every other peripheral clock gate in Amlogic Clock drivers,
* we are using CLK_IGNORE_UNUSED here, so we keep the state of the
* bootloader. The goal is to remove this flag at some point.
* Actually removing it will require some extensive test to be done safely.
*/
#define AXG_AO_GATE(_name, _reg, _bit) \
static struct clk_regmap g12a_aoclk_##_name = { \
.data = &(struct clk_regmap_gate_data) { \
.offset = (_reg), \
.bit_idx = (_bit), \
}, \
.hw.init = &(struct clk_init_data) { \
.name = "g12a_ao_" #_name, \
.ops = &clk_regmap_gate_ops, \
.parent_data = &(const struct clk_parent_data) { \
.fw_name = "mpeg-clk", \
}, \
.num_parents = 1, \
.flags = CLK_IGNORE_UNUSED, \
}, \
}
AXG_AO_GATE(ahb, AO_CLK_GATE0, 0);
AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1);
AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2);
AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3);
AXG_AO_GATE(uart, AO_CLK_GATE0, 4);
AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5);
AXG_AO_GATE(uart2, AO_CLK_GATE0, 6);
AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7);
AXG_AO_GATE(saradc, AO_CLK_GATE0, 8);
AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0);
AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1);
AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2);
AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3);
AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4);
AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5);
static struct clk_regmap g12a_aoclk_cts_oscin = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTI_PWR_CNTL_REG0,
.bit_idx = 14,
},
.hw.init = &(struct clk_init_data){
.name = "cts_oscin",
.ops = &clk_regmap_gate_ro_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xtal",
},
.num_parents = 1,
},
};
static const struct meson_clk_dualdiv_param g12a_32k_div_table[] = {
{
.dual = 1,
.n1 = 733,
.m1 = 8,
.n2 = 732,
.m2 = 11,
}, {}
};
/* 32k_by_oscin clock */
static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 31,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_pre",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cts_oscin.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_RTC_ALT_CLK_CNTL0,
.shift = 0,
.width = 12,
},
.n2 = {
.reg_off = AO_RTC_ALT_CLK_CNTL0,
.shift = 12,
.width = 12,
},
.m1 = {
.reg_off = AO_RTC_ALT_CLK_CNTL1,
.shift = 0,
.width = 12,
},
.m2 = {
.reg_off = AO_RTC_ALT_CLK_CNTL1,
.shift = 12,
.width = 12,
},
.dual = {
.reg_off = AO_RTC_ALT_CLK_CNTL0,
.shift = 28,
.width = 1,
},
.table = g12a_32k_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_pre.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTC_ALT_CLK_CNTL1,
.mask = 0x1,
.shift = 24,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_div.hw,
&g12a_aoclk_32k_by_oscin_pre.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_32k_by_oscin = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_RTC_ALT_CLK_CNTL0,
.bit_idx = 30,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_32k_by_oscin",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_32k_by_oscin_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* cec clock */
static struct clk_regmap g12a_aoclk_cec_pre = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_CEC_CLK_CNTL_REG0,
.bit_idx = 31,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_pre",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cts_oscin.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_cec_div = {
.data = &(struct meson_clk_dualdiv_data){
.n1 = {
.reg_off = AO_CEC_CLK_CNTL_REG0,
.shift = 0,
.width = 12,
},
.n2 = {
.reg_off = AO_CEC_CLK_CNTL_REG0,
.shift = 12,
.width = 12,
},
.m1 = {
.reg_off = AO_CEC_CLK_CNTL_REG1,
.shift = 0,
.width = 12,
},
.m2 = {
.reg_off = AO_CEC_CLK_CNTL_REG1,
.shift = 12,
.width = 12,
},
.dual = {
.reg_off = AO_CEC_CLK_CNTL_REG0,
.shift = 28,
.width = 1,
},
.table = g12a_32k_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_div",
.ops = &meson_clk_dualdiv_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_pre.hw
},
.num_parents = 1,
},
};
static struct clk_regmap g12a_aoclk_cec_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_CEC_CLK_CNTL_REG1,
.mask = 0x1,
.shift = 24,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_div.hw,
&g12a_aoclk_cec_pre.hw,
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_cec = {
.data = &(struct clk_regmap_gate_data){
.offset = AO_CEC_CLK_CNTL_REG0,
.bit_idx = 30,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cec",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_cec_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
.shift = 10,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_cts_rtc_oscin",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .hw = &g12a_aoclk_32k_by_oscin.hw },
{ .fw_name = "ext-32k-0", },
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_clk81 = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_RTI_PWR_CNTL_REG0,
.mask = 0x1,
.shift = 8,
.flags = CLK_MUX_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_clk81",
.ops = &clk_regmap_mux_ro_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "mpeg-clk", },
{ .hw = &g12a_aoclk_cts_rtc_oscin.hw },
},
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_saradc_mux = {
.data = &(struct clk_regmap_mux_data) {
.offset = AO_SAR_CLK,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_mux",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &g12a_aoclk_clk81.hw },
},
.num_parents = 2,
},
};
static struct clk_regmap g12a_aoclk_saradc_div = {
.data = &(struct clk_regmap_div_data) {
.offset = AO_SAR_CLK,
.shift = 0,
.width = 8,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_saradc_mux.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap g12a_aoclk_saradc_gate = {
.data = &(struct clk_regmap_gate_data) {
.offset = AO_SAR_CLK,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data){
.name = "g12a_ao_saradc_gate",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_aoclk_saradc_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const unsigned int g12a_aoclk_reset[] = {
[RESET_AO_IR_IN] = 16,
[RESET_AO_UART] = 17,
[RESET_AO_I2C_M] = 18,
[RESET_AO_I2C_S] = 19,
[RESET_AO_SAR_ADC] = 20,
[RESET_AO_UART2] = 22,
[RESET_AO_IR_OUT] = 23,
};
static struct clk_regmap *g12a_aoclk_regmap[] = {
&g12a_aoclk_ahb,
&g12a_aoclk_ir_in,
&g12a_aoclk_i2c_m0,
&g12a_aoclk_i2c_s0,
&g12a_aoclk_uart,
&g12a_aoclk_prod_i2c,
&g12a_aoclk_uart2,
&g12a_aoclk_ir_out,
&g12a_aoclk_saradc,
&g12a_aoclk_mailbox,
&g12a_aoclk_m3,
&g12a_aoclk_ahb_sram,
&g12a_aoclk_rti,
&g12a_aoclk_m4_fclk,
&g12a_aoclk_m4_hclk,
&g12a_aoclk_cts_oscin,
&g12a_aoclk_32k_by_oscin_pre,
&g12a_aoclk_32k_by_oscin_div,
&g12a_aoclk_32k_by_oscin_sel,
&g12a_aoclk_32k_by_oscin,
&g12a_aoclk_cec_pre,
&g12a_aoclk_cec_div,
&g12a_aoclk_cec_sel,
&g12a_aoclk_cec,
&g12a_aoclk_cts_rtc_oscin,
&g12a_aoclk_clk81,
&g12a_aoclk_saradc_mux,
&g12a_aoclk_saradc_div,
&g12a_aoclk_saradc_gate,
};
static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
.hws = {
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
},
.num = NR_CLKS,
};
static const struct meson_aoclk_data g12a_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
.reset = g12a_aoclk_reset,
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
.clks = g12a_aoclk_regmap,
.hw_data = &g12a_aoclk_onecell_data,
};
static const struct of_device_id g12a_aoclkc_match_table[] = {
{
.compatible = "amlogic,meson-g12a-aoclkc",
.data = &g12a_aoclkc_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, g12a_aoclkc_match_table);
static struct platform_driver g12a_aoclkc_driver = {
.probe = meson_aoclkc_probe,
.driver = {
.name = "g12a-aoclkc",
.of_match_table = g12a_aoclkc_match_table,
},
};
module_platform_driver(g12a_aoclkc_driver);
MODULE_LICENSE("GPL v2");
drivers/clk/meson/g12a-aoclk.h
+31
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@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __G12A_AOCLKC_H
#define __G12A_AOCLKC_H
/*
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
* It has now been decided to expose everything by default in the DT header:
* include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
* to expose, such as the internal muxes and dividers of composite clocks,
* will remain defined here.
*/
#define CLKID_AO_SAR_ADC_DIV 17
#define CLKID_AO_32K_PRE 20
#define CLKID_AO_32K_DIV 21
#define CLKID_AO_32K_SEL 22
#define CLKID_AO_CEC_PRE 24
#define CLKID_AO_CEC_DIV 25
#define CLKID_AO_CEC_SEL 26
#define NR_CLKS 29
#include <dt-bindings/clock/amlogic,g12a-aoclkc.h>
#include <dt-bindings/reset/g12a-aoclkc.h>
#endif /* __G12A_AOCLKC_H */
drivers/clk/meson/g12a.c
+6652
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File diff suppressed because it is too large Load Diff
drivers/clk/meson/g12a.h
+261
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@@ -0,0 +1,261 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __G12A_H
#define __G12A_H
/*
* Clock controller register offsets
*
* Register offsets from the data sheet must be multiplied by 4 before
* adding them to the base address to get the right value.
*/
#define HHI_MIPI_CNTL0 0x000
#define HHI_MIPI_CNTL1 0x004
#define HHI_MIPI_CNTL2 0x008
#define HHI_MIPI_STS 0x00C
#define HHI_GP0_PLL_CNTL0 0x040
#define HHI_GP0_PLL_CNTL1 0x044
#define HHI_GP0_PLL_CNTL2 0x048
#define HHI_GP0_PLL_CNTL3 0x04C
#define HHI_GP0_PLL_CNTL4 0x050
#define HHI_GP0_PLL_CNTL5 0x054
#define HHI_GP0_PLL_CNTL6 0x058
#define HHI_GP0_PLL_STS 0x05C
#define HHI_GP1_PLL_CNTL0 0x060
#define HHI_GP1_PLL_CNTL1 0x064
#define HHI_GP1_PLL_CNTL2 0x068
#define HHI_GP1_PLL_CNTL3 0x06C
#define HHI_GP1_PLL_CNTL4 0x070
#define HHI_GP1_PLL_CNTL5 0x074
#define HHI_GP1_PLL_CNTL6 0x078
#define HHI_GP1_PLL_STS 0x07C
#define HHI_PCIE_PLL_CNTL0 0x098
#define HHI_PCIE_PLL_CNTL1 0x09C
#define HHI_PCIE_PLL_CNTL2 0x0A0
#define HHI_PCIE_PLL_CNTL3 0x0A4
#define HHI_PCIE_PLL_CNTL4 0x0A8
#define HHI_PCIE_PLL_CNTL5 0x0AC
#define HHI_PCIE_PLL_STS 0x0B8
#define HHI_HIFI_PLL_CNTL0 0x0D8
#define HHI_HIFI_PLL_CNTL1 0x0DC
#define HHI_HIFI_PLL_CNTL2 0x0E0
#define HHI_HIFI_PLL_CNTL3 0x0E4
#define HHI_HIFI_PLL_CNTL4 0x0E8
#define HHI_HIFI_PLL_CNTL5 0x0EC
#define HHI_HIFI_PLL_CNTL6 0x0F0
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12C
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_OTHER2 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1A0
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_VIPNANOQ_CLK_CNTL 0x1c8
#define HHI_HDMI_CLK_CNTL 0x1CC
#define HHI_VDEC_CLK_CNTL 0x1E0
#define HHI_VDEC2_CLK_CNTL 0x1E4
#define HHI_VDEC3_CLK_CNTL 0x1E8
#define HHI_VDEC4_CLK_CNTL 0x1EC
#define HHI_HDCP22_CLK_CNTL 0x1F0
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
#define HHI_SYS_CPUB_CLK_CNTL 0x208
#define HHI_VPU_CLKB_CNTL 0x20C
#define HHI_SYS_CPU_CLK_CNTL2 0x210
#define HHI_SYS_CPU_CLK_CNTL3 0x214
#define HHI_SYS_CPU_CLK_CNTL4 0x218
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
#define HHI_SYS_CPU_CLK_CNTL6 0x220
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_WAVE420L_CLK_CNTL 0x268
#define HHI_WAVE420L_CLK_CNTL2 0x26C
#define HHI_MPLL_CNTL0 0x278
#define HHI_MPLL_CNTL1 0x27C
#define HHI_MPLL_CNTL2 0x280
#define HHI_MPLL_CNTL3 0x284
#define HHI_MPLL_CNTL4 0x288
#define HHI_MPLL_CNTL5 0x28c
#define HHI_MPLL_CNTL6 0x290
#define HHI_MPLL_CNTL7 0x294
#define HHI_MPLL_CNTL8 0x298
#define HHI_FIX_PLL_CNTL0 0x2A0
#define HHI_FIX_PLL_CNTL1 0x2A4
#define HHI_FIX_PLL_CNTL3 0x2AC
#define HHI_SYS_PLL_CNTL0 0x2f4
#define HHI_SYS_PLL_CNTL1 0x2f8
#define HHI_SYS_PLL_CNTL2 0x2fc
#define HHI_SYS_PLL_CNTL3 0x300
#define HHI_SYS_PLL_CNTL4 0x304
#define HHI_SYS_PLL_CNTL5 0x308
#define HHI_SYS_PLL_CNTL6 0x30c
#define HHI_HDMI_PLL_CNTL0 0x320
#define HHI_HDMI_PLL_CNTL1 0x324
#define HHI_HDMI_PLL_CNTL2 0x328
#define HHI_HDMI_PLL_CNTL3 0x32c
#define HHI_HDMI_PLL_CNTL4 0x330
#define HHI_HDMI_PLL_CNTL5 0x334
#define HHI_HDMI_PLL_CNTL6 0x338
#define HHI_SPICC_CLK_CNTL 0x3dc
#define HHI_SYS1_PLL_CNTL0 0x380
#define HHI_SYS1_PLL_CNTL1 0x384
#define HHI_SYS1_PLL_CNTL2 0x388
#define HHI_SYS1_PLL_CNTL3 0x38c
#define HHI_SYS1_PLL_CNTL4 0x390
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
#define HHI_BT656_CLK_CNTL 0x3d4 /* 0xf5 offset in datasheet1 */
/*
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
* It has now been decided to expose everything by default in the DT header:
* include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
* to expose, such as the internal muxes and dividers of composite clocks,
* will remain defined here.
*/
#define CLKID_MPEG_SEL 8
#define CLKID_MPEG_DIV 9
#define CLKID_SD_EMMC_A_CLK0_SEL 63
#define CLKID_SD_EMMC_A_CLK0_DIV 64
#define CLKID_SD_EMMC_B_CLK0_SEL 65
#define CLKID_SD_EMMC_B_CLK0_DIV 66
#define CLKID_SD_EMMC_C_CLK0_SEL 67
#define CLKID_SD_EMMC_C_CLK0_DIV 68
#define CLKID_MPLL0_DIV 69
#define CLKID_MPLL1_DIV 70
#define CLKID_MPLL2_DIV 71
#define CLKID_MPLL3_DIV 72
#define CLKID_MPLL_PREDIV 73
#define CLKID_FCLK_DIV2_DIV 75
#define CLKID_FCLK_DIV3_DIV 76
#define CLKID_FCLK_DIV4_DIV 77
#define CLKID_FCLK_DIV5_DIV 78
#define CLKID_FCLK_DIV7_DIV 79
#define CLKID_FCLK_DIV2P5_DIV 100
#define CLKID_FIXED_PLL_DCO 101
#define CLKID_SYS_PLL_DCO 102
#define CLKID_GP0_PLL_DCO 103
#define CLKID_HIFI_PLL_DCO 104
#define CLKID_VPU_0_DIV 111
#define CLKID_VPU_1_DIV 114
#define CLKID_VAPB_0_DIV 118
#define CLKID_VAPB_1_DIV 121
#define CLKID_HDMI_PLL_DCO 125
#define CLKID_HDMI_PLL_OD 126
#define CLKID_HDMI_PLL_OD2 127
#define CLKID_VID_PLL_SEL 130
#define CLKID_VID_PLL_DIV 131
#define CLKID_VCLK_SEL 132
#define CLKID_VCLK2_SEL 133
#define CLKID_VCLK_INPUT 134
#define CLKID_VCLK2_INPUT 135
#define CLKID_VCLK_DIV 136
#define CLKID_VCLK2_DIV 137
#define CLKID_VCLK_DIV2_EN 140
#define CLKID_VCLK_DIV4_EN 141
#define CLKID_VCLK_DIV6_EN 142
#define CLKID_VCLK_DIV12_EN 143
#define CLKID_VCLK2_DIV2_EN 144
#define CLKID_VCLK2_DIV4_EN 145
#define CLKID_VCLK2_DIV6_EN 146
#define CLKID_VCLK2_DIV12_EN 147
#define CLKID_CTS_ENCI_SEL 158
#define CLKID_CTS_ENCP_SEL 159
#define CLKID_CTS_VDAC_SEL 160
#define CLKID_HDMI_TX_SEL 161
#define CLKID_HDMI_SEL 166
#define CLKID_HDMI_DIV 167
#define CLKID_MALI_0_DIV 170
#define CLKID_MALI_1_DIV 173
#define CLKID_MPLL_50M_DIV 176
#define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180
#define CLKID_CPU_CLK_DYN0_DIV 181
#define CLKID_CPU_CLK_DYN0 182
#define CLKID_CPU_CLK_DYN1_SEL 183
#define CLKID_CPU_CLK_DYN1_DIV 184
#define CLKID_CPU_CLK_DYN1 185
#define CLKID_CPU_CLK_DIV16_EN 188
#define CLKID_CPU_CLK_DIV16 189
#define CLKID_CPU_CLK_APB_DIV 190
#define CLKID_CPU_CLK_APB 191
#define CLKID_CPU_CLK_ATB_DIV 192
#define CLKID_CPU_CLK_ATB 193
#define CLKID_CPU_CLK_AXI_DIV 194
#define CLKID_CPU_CLK_AXI 195
#define CLKID_CPU_CLK_TRACE_DIV 196
#define CLKID_CPU_CLK_TRACE 197
#define CLKID_PCIE_PLL_DCO 198
#define CLKID_PCIE_PLL_DCO_DIV2 199
#define CLKID_PCIE_PLL_OD 200
#define CLKID_VDEC_1_SEL 202
#define CLKID_VDEC_1_DIV 203
#define CLKID_VDEC_HEVC_SEL 205
#define CLKID_VDEC_HEVC_DIV 206
#define CLKID_VDEC_HEVCF_SEL 208
#define CLKID_VDEC_HEVCF_DIV 209
#define CLKID_TS_DIV 211
#define CLKID_SYS1_PLL_DCO 213
#define CLKID_SYS1_PLL 214
#define CLKID_SYS1_PLL_DIV16_EN 215
#define CLKID_SYS1_PLL_DIV16 216
#define CLKID_CPUB_CLK_DYN0_SEL 217
#define CLKID_CPUB_CLK_DYN0_DIV 218
#define CLKID_CPUB_CLK_DYN0 219
#define CLKID_CPUB_CLK_DYN1_SEL 220
#define CLKID_CPUB_CLK_DYN1_DIV 221
#define CLKID_CPUB_CLK_DYN1 222
#define CLKID_CPUB_CLK_DYN 223
#define CLKID_CPUB_CLK_DIV16_EN 225
#define CLKID_CPUB_CLK_DIV16 226
#define CLKID_CPUB_CLK_DIV2 227
#define CLKID_CPUB_CLK_DIV3 228
#define CLKID_CPUB_CLK_DIV4 229
#define CLKID_CPUB_CLK_DIV5 230
#define CLKID_CPUB_CLK_DIV6 231
#define CLKID_CPUB_CLK_DIV7 232
#define CLKID_CPUB_CLK_DIV8 233
#define CLKID_CPUB_CLK_APB_SEL 234
#define CLKID_CPUB_CLK_APB 235
#define CLKID_CPUB_CLK_ATB_SEL 236
#define CLKID_CPUB_CLK_ATB 237
#define CLKID_CPUB_CLK_AXI_SEL 238
#define CLKID_CPUB_CLK_AXI 239
#define CLKID_CPUB_CLK_TRACE_SEL 240
#define CLKID_CPUB_CLK_TRACE 241
#define CLKID_GP1_PLL_DCO 242
#define CLKID_DSU_CLK_DYN0_SEL 244
#define CLKID_DSU_CLK_DYN0_DIV 245
#define CLKID_DSU_CLK_DYN0 246
#define CLKID_DSU_CLK_DYN1_SEL 247
#define CLKID_DSU_CLK_DYN1_DIV 248
#define CLKID_DSU_CLK_DYN1 249
#define CLKID_DSU_CLK_DYN 250
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/amlogic,g12a-clkc.h>
#define NR_CLKS CLKID_END
#endif /* __G12A_H */
drivers/clk/meson/meson-aoclk.c
+14
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@@ -14,6 +14,8 @@
#include <linux/reset-controller.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/clkdev.h>
#include <linux/slab.h>
#include "meson-aoclk.h"
@@ -79,8 +81,20 @@ int meson_aoclkc_probe(struct platform_device *pdev)
dev_err(dev, "Clock registration failed\n");
return ret;
}
#ifdef CONFIG_AMLOGIC_CLK_DEBUG
ret = devm_clk_hw_register_clkdev(dev, data->hw_data->hws[clkid],
NULL,
clk_hw_get_name(data->hw_data->hws[clkid]));
if (ret < 0) {
dev_err(dev, "Failed to clkdev register: %d\n", ret);
return ret;
}
#endif
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
(void *)data->hw_data);
}
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
drivers/clk/meson/meson-clk-measure.c
+137
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@@ -2158,6 +2158,130 @@ static struct meson_msr_id clk_msr_t5m[] __initdata = {
CLK_MSR_ID(226, "sar_adc_clk_o"),
CLK_MSR_ID(227, "jtag_tck_i_pad"),
CLK_MSR_ID(228, "dac_ck0"),
static struct meson_msr_id clk_msr_g12b[] __initdata = {
CLK_MSR_ID(0, "am_ring_osc_clk_out_ee[0]"),
CLK_MSR_ID(1, "am_ring_osc_clk_out_ee[1]"),
CLK_MSR_ID(2, "am_ring_osc_clk_out_ee[2]"),
CLK_MSR_ID(3, "sys_cpu_ring_osc_clk[0]"),
CLK_MSR_ID(4, "gp0_pll_clk"),
CLK_MSR_ID(6, "cts_enci_clk"),
CLK_MSR_ID(7, "clk81"),
CLK_MSR_ID(8, "cts_encp_clk"),
CLK_MSR_ID(9, "cts_encl_clk"),
CLK_MSR_ID(10, "cts_vdac_clk"),
CLK_MSR_ID(11, "mac_eth_tx_clk"),
CLK_MSR_ID(12, "hifi_pll_clk"),
CLK_MSR_ID(13, "mod_tcon_clko"),
CLK_MSR_ID(14, "cts_FEC_CLK_0"),
CLK_MSR_ID(15, "cts_FEC_CLK_1"),
CLK_MSR_ID(16, "cts_FEC_CLK_2"),
CLK_MSR_ID(17, "sys_pll_div16"),
CLK_MSR_ID(18, "sys_cpu_clk_div16"),
CLK_MSR_ID(19, "lcd_an_clk_ph2"),
CLK_MSR_ID(20, "rtc_osc_clk_out"),
CLK_MSR_ID(21, "lcd_an_clk_ph3"),
CLK_MSR_ID(22, "mac_eth_phy_ref_clk"),
CLK_MSR_ID(23, "mpll_clk_50m"),
CLK_MSR_ID(24, "cts_eth_clk125Mhz"),
CLK_MSR_ID(25, "cts_eth_clk_rmii"),
CLK_MSR_ID(26, "sc_clk_int"),
CLK_MSR_ID(27, "co_clkin_to_mac"),
CLK_MSR_ID(28, "cts_sar_adc_clk"),
CLK_MSR_ID(29, "pcie_clk_inp"),
CLK_MSR_ID(30, "pcie_clk_inn"),
CLK_MSR_ID(31, "mpll_clk_test_out"),
CLK_MSR_ID(32, "cts_vdec_clk"),
CLK_MSR_ID(33, "sys_cpu_ring_osc_clk[1]"),
CLK_MSR_ID(34, "eth_mppll_50m_ckout"),
CLK_MSR_ID(35, "cts_mali_clk"),
CLK_MSR_ID(36, "cts_hdmi_tx_pixel_clk"),
CLK_MSR_ID(37, "cts_cdac_clk_c"),
CLK_MSR_ID(38, "cts_vdin_meas_clk"),
CLK_MSR_ID(39, "cts_bt656_clk0"),
CLK_MSR_ID(41, "mac_eth_rx_clk_rmii"),
CLK_MSR_ID(42, "mp0_clk_out"),
CLK_MSR_ID(43, "fclk_div5"),
CLK_MSR_ID(44, "cts_pwm_B_clk"),
CLK_MSR_ID(45, "cts_pwm_A_clk"),
CLK_MSR_ID(46, "cts_vpu_clk"),
CLK_MSR_ID(47, "ddr_dpll_pt_clk"),
CLK_MSR_ID(48, "mp1_clk_out"),
CLK_MSR_ID(49, "mp2_clk_out"),
CLK_MSR_ID(50, "mp3_clk_out"),
CLK_MSR_ID(51, "cts_sd_emmc_clk_C"),
CLK_MSR_ID(52, "cts_sd_emmc_clk_B"),
CLK_MSR_ID(53, "cts_sd_emmc_clk_A"),
CLK_MSR_ID(54, "cts_vpu_clkc"),
CLK_MSR_ID(55, "vid_pll_div_clk_out"),
CLK_MSR_ID(56, "cts_wave420l_aclk"),
CLK_MSR_ID(57, "cts_wave420l_cclk"),
CLK_MSR_ID(58, "cts_wave420l_bclk"),
CLK_MSR_ID(59, "cts_hcodec_clk"),
CLK_MSR_ID(61, "gpio_clk_msr"),
CLK_MSR_ID(62, "cts_hevcb_clk"),
CLK_MSR_ID(63, "cts_dsi_meas_clk"),
CLK_MSR_ID(64, "cts_spicc_1_clk"),
CLK_MSR_ID(65, "cts_spicc_0_clk"),
CLK_MSR_ID(66, "cts_vid_lock_clk"),
CLK_MSR_ID(67, "cts_dsi_phy_clk"),
CLK_MSR_ID(68, "cts_hdcp22_esmclk"),
CLK_MSR_ID(69, "cts_hdcp22_skpclk"),
CLK_MSR_ID(70, "cts_pwm_F_clk"),
CLK_MSR_ID(71, "cts_pwm_E_clk"),
CLK_MSR_ID(72, "cts_pwm_D_clk"),
CLK_MSR_ID(73, "cts_pwm_C_clk"),
CLK_MSR_ID(74, "cts_mipi_csi_phy_clk"),
CLK_MSR_ID(75, "cts_hevcf_clk"),
CLK_MSR_ID(76, "cts_cci_clk"),
CLK_MSR_ID(77, "rng_ring_osc_clk[0]"),
CLK_MSR_ID(78, "rng_ring_osc_clk[1]"),
CLK_MSR_ID(79, "rng_ring_osc_clk[2]"),
CLK_MSR_ID(80, "rng_ring_osc_clk[3]"),
CLK_MSR_ID(81, "cts_vapbclk"),
CLK_MSR_ID(82, "cts_ge2d_clk"),
CLK_MSR_ID(83, "co_rx_clk"),
CLK_MSR_ID(84, "co_tx_clk"),
CLK_MSR_ID(85, "cts_vipnanoq_axi_clk"),
CLK_MSR_ID(86, "cts_vipnanoq_core_clk"),
CLK_MSR_ID(88, "cts_mipi_isp_clk"),
CLK_MSR_ID(89, "HDMI_CLK_TODIG"),
CLK_MSR_ID(90, "cts_hdmitx_sys_clk"),
CLK_MSR_ID(91, "sys_cpuB_clk_div16"),
CLK_MSR_ID(92, "sys_pllB_div16"),
CLK_MSR_ID(94, "eth_phy_rxclk"),
CLK_MSR_ID(95, "eth_phy_plltxclk"),
CLK_MSR_ID(96, "cts_vpu_clkb"),
CLK_MSR_ID(97, "cts_vpu_clkb_tmp"),
CLK_MSR_ID(98, "cts_ts_clk"),
CLK_MSR_ID(99, "am_ring_osc_clk_out_ee[3]"),
CLK_MSR_ID(100, "am_ring_osc_clk_out_ee[4]"),
CLK_MSR_ID(101, "am_ring_osc_clk_out_ee[5]"),
CLK_MSR_ID(102, "am_ring_osc_clk_out_ee[6]"),
CLK_MSR_ID(103, "am_ring_osc_clk_out_ee[7]"),
CLK_MSR_ID(104, "am_ring_osc_clk_out_ee[8]"),
CLK_MSR_ID(105, "am_ring_osc_clk_out_ee[9]"),
CLK_MSR_ID(106, "ephy_test_clk"),
CLK_MSR_ID(107, "au_dac_clk_g128x"),
CLK_MSR_ID(108, "c_alocker_in_clk"),
CLK_MSR_ID(109, "c_alocker_out_clk"),
CLK_MSR_ID(110, "audio_tdmout_c_sclk"),
CLK_MSR_ID(111, "audio_tdmout_b_sclk"),
CLK_MSR_ID(112, "audio_tdmout_a_sclk"),
CLK_MSR_ID(113, "audio_tdmin_lb_sclk"),
CLK_MSR_ID(114, "audio_tdmin_c_sclk"),
CLK_MSR_ID(115, "audio_tdmin_b_sclk"),
CLK_MSR_ID(116, "audio_tdmin_a_sclk"),
CLK_MSR_ID(117, "audio_resample_clk"),
CLK_MSR_ID(118, "audio_pdm_sysclk"),
CLK_MSR_ID(119, "audio_spdifout_b_mst_clk"),
CLK_MSR_ID(120, "audio_spdifout_mst_clk"),
CLK_MSR_ID(121, "audio_spdifin_mst_clk"),
CLK_MSR_ID(122, "mod_audio_pdm_dclk_o"),
CLK_MSR_ID(123, "cts_gdc_axi_clk"),
CLK_MSR_ID(124, "cts_gdc_core_clk"),
CLK_MSR_ID(125, "mipi_csi_phy0_clk_out"),
CLK_MSR_ID(126, "mipi_csi_phy1_clk_out"),
};
static int meson_measure_id(struct meson_msr_id *clk_msr_id,
@@ -2535,6 +2659,15 @@ static struct meson_msr_data meson_t5m_data __initdata = {
.reg2_offset = 0x8,
};
static struct meson_msr_data meson_g12b_data __initdata = {
.msr_table = (struct meson_msr_id *)&clk_msr_g12b,
.table_size = ARRAY_SIZE(clk_msr_g12b),
.duty_offset = 0x0,
.reg0_offset = 0x4,
.reg1_offset = 0x8,
.reg2_offset = 0xc,
};
static const struct of_device_id meson_msr_match_table[] = {
#ifndef CONFIG_AMLOGIC_REMOVE_OLD
{
@@ -2615,6 +2748,10 @@ static const struct of_device_id meson_msr_match_table[] = {
.compatible = "amlogic,meson-t5m-clk-measure",
.data = &meson_t5m_data,
},
{
.compatible = "amlogic,meson-g12b-clk-measure",
.data = &meson_g12b_data,
},
{ /* sentinel */ }
};
drivers/clk/meson/meson-eeclk.c
+13
View File
@@ -9,6 +9,7 @@
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/clkdev.h>
#include "clk-regmap.h"
#include "meson-eeclk.h"
@@ -49,8 +50,20 @@ int meson_eeclkc_probe(struct platform_device *pdev)
dev_err(dev, "Clock registration failed\n");
return ret;
}
#ifdef CONFIG_AMLOGIC_CLK_DEBUG
ret = devm_clk_hw_register_clkdev(dev, data->hw_onecell_data->hws[i],
NULL,
clk_hw_get_name(data->hw_onecell_data->hws[i]));
if (ret < 0) {
dev_err(dev, "Failed to clkdev register: %d\n", ret);
return ret;
}
#endif
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
data->hw_onecell_data);
}
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
include/dt-bindings/clock/amlogic,g12a-aoclkc.h
+32
View File
@@ -0,0 +1,32 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define CLKID_AO_AHB 0
#define CLKID_AO_IR_IN 1
#define CLKID_AO_I2C_M0 2
#define CLKID_AO_I2C_S0 3
#define CLKID_AO_UART 4
#define CLKID_AO_PROD_I2C 5
#define CLKID_AO_UART2 6
#define CLKID_AO_IR_OUT 7
#define CLKID_AO_SAR_ADC 8
#define CLKID_AO_MAILBOX 9
#define CLKID_AO_M3 10
#define CLKID_AO_AHB_SRAM 11
#define CLKID_AO_RTI 12
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28
#endif
include/dt-bindings/clock/amlogic,g12a-clkc.h
+211 -306
View File
@@ -6,313 +6,218 @@
#ifndef __G12A_CLKC_H
#define __G12A_CLKC_H
/*
* CLKID index values
*/
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
#define CLKID_MPLL2 13
#define CLKID_MPLL3 14
#define CLKID_DDR 15
#define CLKID_DOS 16
#define CLKID_AUDIO_LOCKER 17
#define CLKID_MIPI_DSI_HOST 18
#define CLKID_ETH_PHY 19
#define CLKID_ISA 20
#define CLKID_PL301 21
#define CLKID_PERIPHS 22
#define CLKID_SPICC0 23
#define CLKID_I2C 24
#define CLKID_SANA 25
#define CLKID_SD 26
#define CLKID_RNG0 27
#define CLKID_UART0 28
#define CLKID_SPICC1 29
#define CLKID_HIU_IFACE 30
#define CLKID_MIPI_DSI_PHY 31
#define CLKID_ASSIST_MISC 32
#define CLKID_SD_EMMC_A 33
#define CLKID_SD_EMMC_B 34
#define CLKID_SD_EMMC_C 35
#define CLKID_AUDIO_CODEC 36
#define CLKID_AUDIO 37
#define CLKID_ETH 38
#define CLKID_DEMUX 39
#define CLKID_AUDIO_IFIFO 40
#define CLKID_ADC 41
#define CLKID_UART1 42
#define CLKID_G2D 43
#define CLKID_RESET 44
#define CLKID_PCIE_COMB 45
#define CLKID_PARSER 46
#define CLKID_USB 47
#define CLKID_PCIE_PHY 48
#define CLKID_AHB_ARB0 49
#define CLKID_AHB_DATA_BUS 50
#define CLKID_AHB_CTRL_BUS 51
#define CLKID_HTX_HDCP22 52
#define CLKID_HTX_PCLK 53
#define CLKID_BT656 54
#define CLKID_USB1_DDR_BRIDGE 55
#define CLKID_MMC_PCLK 56
#define CLKID_UART2 57
#define CLKID_VPU_INTR 58
#define CLKID_GIC 59
#define CLKID_SD_EMMC_A_CLK0 60
#define CLKID_SD_EMMC_B_CLK0 61
#define CLKID_SD_EMMC_C_CLK0 62
#define CLKID_SD_EMMC_A_CLK0_SEL 63
#define CLKID_SD_EMMC_A_CLK0_DIV 64
#define CLKID_SD_EMMC_B_CLK0_SEL 65
#define CLKID_SD_EMMC_B_CLK0_DIV 66
#define CLKID_SD_EMMC_C_CLK0_SEL 67
#define CLKID_SD_EMMC_C_CLK0_DIV 68
#define CLKID_HIFI_PLL 74
#define CLKID_VCLK2_VENCI0 80
#define CLKID_VCLK2_VENCI1 81
#define CLKID_VCLK2_VENCP0 82
#define CLKID_VCLK2_VENCP1 83
#define CLKID_VCLK2_VENCT0 84
#define CLKID_VCLK2_VENCT1 85
#define CLKID_VCLK2_OTHER 86
#define CLKID_VCLK2_ENCI 87
#define CLKID_VCLK2_ENCP 88
#define CLKID_DAC_CLK 89
#define CLKID_AOCLK 90
#define CLKID_IEC958 91
#define CLKID_ENC480P 92
#define CLKID_RNG1 93
#define CLKID_VCLK2_ENCT 94
#define CLKID_VCLK2_ENCL 95
#define CLKID_VCLK2_VENCLMMC 96
#define CLKID_VCLK2_VENCL 97
#define CLKID_VCLK2_OTHER1 98
#define CLKID_FCLK_DIV2P5 99
#define CLKID_DMA 105
#define CLKID_EFUSE 106
#define CLKID_ROM_BOOT 107
#define CLKID_RESET_SEC 108
#define CLKID_SEC_AHB_APB3 109
#define CLKID_VPU_0_SEL 110
#define CLKID_VPU_0 112
#define CLKID_VPU_1_SEL 113
#define CLKID_VPU_1 115
#define CLKID_VPU 116
#define CLKID_VAPB_0_SEL 117
#define CLKID_VAPB_0 119
#define CLKID_VAPB_1_SEL 120
#define CLKID_VAPB_1 122
#define CLKID_VAPB_SEL 123
#define CLKID_VAPB 124
#define CLKID_HDMI_PLL 128
#define CLKID_VID_PLL 129
#define CLKID_VCLK 138
#define CLKID_VCLK2 139
#define CLKID_VCLK_DIV1 148
#define CLKID_VCLK_DIV2 149
#define CLKID_VCLK_DIV4 150
#define CLKID_VCLK_DIV6 151
#define CLKID_VCLK_DIV12 152
#define CLKID_VCLK2_DIV1 153
#define CLKID_VCLK2_DIV2 154
#define CLKID_VCLK2_DIV4 155
#define CLKID_VCLK2_DIV6 156
#define CLKID_VCLK2_DIV12 157
#define CLKID_CTS_ENCI 162
#define CLKID_CTS_ENCP 163
#define CLKID_CTS_VDAC 164
#define CLKID_HDMI_TX 165
#define CLKID_HDMI 168
#define CLKID_MALI_0_SEL 169
#define CLKID_MALI_0 171
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK_DYN 186
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF 210
#define CLKID_TS 212
#define CLKID_CPUB_CLK 224
#define CLKID_GP1_PLL 243
#define CLKID_DSU_CLK_FINAL 251
#define CLKID_DSU_CLK 252
#define CLKID_CPU1_CLK 253
#define CLKID_CPU2_CLK 254
#define CLKID_CPU3_CLK 255
#define CLKID_PCIE_HCSL 256
#define CLKID_PCIE_BGP 257
/* Media clocks */
#define MEDIA_BASE (258 + 1)
#define CLKID_DSI_MEAS_MUX (MEDIA_BASE + 0)
#define CLKID_DSI_MEAS_DIV (MEDIA_BASE + 1)
#define CLKID_DSI_MEAS (MEDIA_BASE + 2)
#define CLKID_VDEC_P1_MUX (MEDIA_BASE + 3)
#define CLKID_VDEC_P1_DIV (MEDIA_BASE + 4)
#define CLKID_VDEC_P1 (MEDIA_BASE + 5)
#define CLKID_VDEC_MUX (MEDIA_BASE + 6)
#define CLKID_HCODEC_P0_MUX (MEDIA_BASE + 7)
#define CLKID_HCODEC_P0_DIV (MEDIA_BASE + 8)
#define CLKID_HCODEC_P0 (MEDIA_BASE + 9)
#define CLKID_HCODEC_P1_MUX (MEDIA_BASE + 10)
#define CLKID_HCODEC_P1_DIV (MEDIA_BASE + 11)
#define CLKID_HCODEC_P1 (MEDIA_BASE + 12)
#define CLKID_HCODEC_MUX (MEDIA_BASE + 13)
#define CLKID_HEVC_P1_MUX (MEDIA_BASE + 14)
#define CLKID_HEVC_P1_DIV (MEDIA_BASE + 15)
#define CLKID_HEVC_P1 (MEDIA_BASE + 16)
#define CLKID_HEVC_MUX (MEDIA_BASE + 17)
#define CLKID_HEVCF_P1_MUX (MEDIA_BASE + 18)
#define CLKID_HEVCF_P1_DIV (MEDIA_BASE + 19)
#define CLKID_HEVCF_P1 (MEDIA_BASE + 20)
#define CLKID_HEVCF_MUX (MEDIA_BASE + 21)
#define CLKID_VPU_CLKB_TMP_MUX (MEDIA_BASE + 22)
#define CLKID_VPU_CLKB_TMP_DIV (MEDIA_BASE + 23)
#define CLKID_VPU_CLKB_TMP (MEDIA_BASE + 24)
#define CLKID_VPU_CLKB_DIV (MEDIA_BASE + 25)
#define CLKID_VPU_CLKB (MEDIA_BASE + 26)
#define CLKID_VPU_CLKC_P0_MUX (MEDIA_BASE + 27)
#define CLKID_VPU_CLKC_P0_DIV (MEDIA_BASE + 28)
#define CLKID_VPU_CLKC_P0 (MEDIA_BASE + 29)
#define CLKID_VPU_CLKC_P1_MUX (MEDIA_BASE + 30)
#define CLKID_VPU_CLKC_P1_DIV (MEDIA_BASE + 31)
#define CLKID_VPU_CLKC_P1 (MEDIA_BASE + 32)
#define CLKID_VPU_CLKC_MUX (MEDIA_BASE + 33)
#define CLKID_VDIN_MEAS_MUX (MEDIA_BASE + 34)
#define CLKID_VDIN_MEAS_DIV (MEDIA_BASE + 35)
#define CLKID_VDIN_MEAS_GATE (MEDIA_BASE + 36)
#define CLKID_WAVE_A_SEL (MEDIA_BASE + 37)
#define CLKID_WAVE_A_DIV (MEDIA_BASE + 38)
#define CLKID_WAVE_A_CLK (MEDIA_BASE + 39)
#define CLKID_WAVE_B_SEL (MEDIA_BASE + 40)
#define CLKID_WAVE_B_DIV (MEDIA_BASE + 41)
#define CLKID_WAVE_B_CLK (MEDIA_BASE + 42)
#define CLKID_WAVE_C_SEL (MEDIA_BASE + 43)
#define CLKID_WAVE_C_DIV (MEDIA_BASE + 44)
#define CLKID_WAVE_C_CLK (MEDIA_BASE + 45)
#define CLKID_VIPNANOQ_CORE_MUX (MEDIA_BASE + 46)
#define CLKID_VIPNANOQ_CORE_DIV (MEDIA_BASE + 47)
#define CLKID_VIPNANOQ_CORE_GATE (MEDIA_BASE + 48)
#define CLKID_VIPNANOQ_AXI_MUX (MEDIA_BASE + 49)
#define CLKID_VIPNANOQ_AXI_DIV (MEDIA_BASE + 50)
#define CLKID_VIPNANOQ_AXI_GATE (MEDIA_BASE + 51)
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_HIFI_PLL 8
#define CLKID_MPEG_SEL 9
#define CLKID_MPEG_DIV 10
#define CLKID_CLK81 11
#define CLKID_MPLL0 12
#define CLKID_MPLL1 13
#define CLKID_MPLL2 14
#define CLKID_MPLL3 15
#define CLKID_CPU_FCLK_P00 16
#define CLKID_CPU_FCLK_P01 17
#define CLKID_CPU_FCLK_P0 18
#define CLKID_CPU_FCLK_P10 19
#define CLKID_CPU_FCLK_P11 20
#define CLKID_CPU_FCLK_P1 21
#define CLKID_CPU_FCLK_P 22
#define CLKID_CPU_CLK 23
#define CLKID_PCIE_PLL 24
#define CLKID_PCIE_MUX 25
#define CLKID_PCIE_REF 26
#define CLKID_PCIE_INPUT_GATE 27
#define CLKID_PCIE_CML_EN0 28
#define CLKID_PCIE_CML_EN1 29
#define CLKID_MIPI_ENABLE_GATE 30
#define CLKID_MIPI_BANDGAP_GATE 31
#define CLKID_FCLK_DIV2P5 32
#define CLKID_PCIE_HCSL 33
/*misc clocks*/
#define MISC_BASE (MEDIA_BASE + 52)
#define CLKID_SPICC0_MUX (MISC_BASE + 0)
#define CLKID_SPICC0_DIV (MISC_BASE + 1)
#define CLKID_SPICC0_GATE (MISC_BASE + 2)
#define CLKID_SPICC1_MUX (MISC_BASE + 3)
#define CLKID_SPICC1_DIV (MISC_BASE + 4)
#define CLKID_SPICC1_GATE (MISC_BASE + 5)
#define CLKID_BT656_MUX (MISC_BASE + 6)
#define CLKID_BT656_DIV (MISC_BASE + 7)
#define CLKID_BT656_GATE (MISC_BASE + 8)
/*HHI_GCLK_MPEG0: 0x50*/
#define GATE_BASE0 34
#define CLKID_DDR (GATE_BASE0 + 0)
#define CLKID_DOS (GATE_BASE0 + 1)
#define CLKID_AUDIO_LOCKER (GATE_BASE0 + 2)
#define CLKID_MIPI_DSI_HOST (GATE_BASE0 + 3)
#define CLKID_ETH_PHY (GATE_BASE0 + 4)
#define CLKID_ISA (GATE_BASE0 + 5)
#define CLKID_PL301 (GATE_BASE0 + 6)
#define CLKID_PERIPHS (GATE_BASE0 + 7)
#define CLKID_SPICC0 (GATE_BASE0 + 8)
#define CLKID_I2C (GATE_BASE0 + 9)
#define CLKID_SANA (GATE_BASE0 + 10)
#define CLKID_SD (GATE_BASE0 + 11)
#define CLKID_RNG0 (GATE_BASE0 + 12)
#define CLKID_UART0 (GATE_BASE0 + 13)
#define CLKID_SPICC1 (GATE_BASE0 + 14)
#define CLKID_HIU_REG (GATE_BASE0 + 15)
#define CLKID_MIPI_DSI_PHY (GATE_BASE0 + 16)
#define CLKID_ASSIST_MISC (GATE_BASE0 + 17)
#define CLKID_SD_EMMC_A (GATE_BASE0 + 18)
#define CLKID_SD_EMMC_B (GATE_BASE0 + 19)
#define CLKID_SD_EMMC_C (GATE_BASE0 + 20)
#define CLKID_ACODEC (GATE_BASE0 + 21)
/*HHI_GCLK_MPEG1: 0x51*/
#define GATE_BASE1 (GATE_BASE0 + 22)
#define CLKID_AUDIO (GATE_BASE1 + 0)
#define CLKID_ETH_CORE (GATE_BASE1 + 1)
#define CLKID_DEMUX (GATE_BASE1 + 2)
#define CLKID_AIFIFO (GATE_BASE1 + 3)
#define CLKID_ADC (GATE_BASE1 + 4)
#define CLKID_UART1 (GATE_BASE1 + 5)
#define CLKID_G2D (GATE_BASE1 + 6)
#define CLKID_RESET (GATE_BASE1 + 7)
#define CLKID_PCIE_COMB (GATE_BASE1 + 8)
#define CLKID_DOS_PARSER (GATE_BASE1 + 9)
#define CLKID_USB_GENERAL (GATE_BASE1 + 10)
#define CLKID_PCIE_PHY (GATE_BASE1 + 11)
#define CLKID_AHB_ARB0 (GATE_BASE1 + 12)
/*HHI_GCLK_MPEG2: 0x52*/
#define GATE_BASE2 (GATE_BASE1 + 13)
#define CLKID_AHB_DATA_BUS (GATE_BASE2 + 0)
#define CLKID_AHB_CTRL_BUS (GATE_BASE2 + 1)
#define CLKID_HTX_HDCP22 (GATE_BASE2 + 2)
#define CLKID_HTX_PCLK (GATE_BASE2 + 3)
#define CLKID_BT656 (GATE_BASE2 + 4)
#define CLKID_USB1_TO_DDR (GATE_BASE2 + 5)
#define CLKID_MMC_PCLK (GATE_BASE2 + 6)
#define CLKID_UART2 (GATE_BASE2 + 7)
#define CLKID_VPU_INTR (GATE_BASE2 + 8)
#define CLKID_GIC (GATE_BASE2 + 9)
/*HHI_GCLK_OTHER: 0x54*/
#define GATE_BASE3 (GATE_BASE2 + 10)
#define CLKID_VCLK2_VENCI0 (GATE_BASE3 + 0)
#define CLKID_VCLK2_VENCI1 (GATE_BASE3 + 1)
#define CLKID_VCLK2_VENCP0 (GATE_BASE3 + 2)
#define CLKID_VCLK2_VENCP1 (GATE_BASE3 + 3)
#define CLKID_VCLK2_VENCT0 (GATE_BASE3 + 4)
#define CLKID_VCLK2_VENCT1 (GATE_BASE3 + 5)
#define CLKID_VCLK2_OTHER (GATE_BASE3 + 6)
#define CLKID_VCLK2_ENCI (GATE_BASE3 + 7)
#define CLKID_VCLK2_ENCP (GATE_BASE3 + 8)
#define CLKID_DAC_CLK (GATE_BASE3 + 9)
#define CLKID_AOCLK_GATE (GATE_BASE3 + 10)
#define CLKID_IEC958_GATE (GATE_BASE3 + 11)
#define CLKID_ENC480P (GATE_BASE3 + 12)
#define CLKID_RNG1 (GATE_BASE3 + 13)
#define CLKID_VCLK2_ENCT (GATE_BASE3 + 14)
#define CLKID_VCLK2_ENCL (GATE_BASE3 + 15)
#define CLKID_VCLK2_VENCLMMC (GATE_BASE3 + 16)
#define CLKID_VCLK2_VENCL (GATE_BASE3 + 17)
#define CLKID_VCLK2_OTHER1 (GATE_BASE3 + 18)
/*HHI_GCLK_SP_MPEG: 0x55*/
#define GATE_BASE4 (GATE_BASE3 + 19)
#define CLKID_EFUSE (GATE_BASE4 + 0)
#define GATE_AO_BASE (GATE_BASE4 + 1)
#define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0)
#define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1)
#define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2)
#define CLKID_AO_IFACE (GATE_AO_BASE + 3)
#define CLKID_AO_I2C (GATE_AO_BASE + 4)
#define OTHER_BASE (GATE_AO_BASE + 5)
#define CLKID_SD_EMMC_A_P0_MUX (OTHER_BASE + 0)
#define CLKID_SD_EMMC_A_P0_DIV (OTHER_BASE + 1)
#define CLKID_SD_EMMC_A_P0_GATE (OTHER_BASE + 2)
#define CLKID_SD_EMMC_A_P0_COMP (OTHER_BASE + 3)
#define CLKID_SD_EMMC_B_P0_MUX (OTHER_BASE + 4)
#define CLKID_SD_EMMC_B_P0_DIV (OTHER_BASE + 5)
#define CLKID_SD_EMMC_B_P0_GATE (OTHER_BASE + 6)
#define CLKID_SD_EMMC_B_P0_COMP (OTHER_BASE + 7)
#define CLKID_SD_EMMC_C_P0_MUX (OTHER_BASE + 8)
#define CLKID_SD_EMMC_C_P0_DIV (OTHER_BASE + 9)
#define CLKID_SD_EMMC_C_P0_GATE (OTHER_BASE + 10)
#define CLKID_SD_EMMC_C_P0_COMP (OTHER_BASE + 11)
#define CLKID_SD_EMMC_B_MUX (OTHER_BASE + 12)
#define CLKID_SD_EMMC_B_DIV (OTHER_BASE + 13)
#define CLKID_SD_EMMC_B_GATE (OTHER_BASE + 14)
#define CLKID_SD_EMMC_B_COMP (OTHER_BASE + 15)
#define CLKID_SD_EMMC_C_MUX (OTHER_BASE + 16)
#define CLKID_SD_EMMC_C_DIV (OTHER_BASE + 17)
#define CLKID_SD_EMMC_C_GATE (OTHER_BASE + 18)
#define CLKID_SD_EMMC_C_COMP (OTHER_BASE + 19)
#define CLKID_GPU_BASE (OTHER_BASE + 20)
#define CLKID_GPU_P0_MUX (CLKID_GPU_BASE + 0)
#define CLKID_GPU_P0_DIV (CLKID_GPU_BASE + 1)
#define CLKID_GPU_P0_GATE (CLKID_GPU_BASE + 2)
#define CLKID_GPU_P0_COMP (CLKID_GPU_BASE + 3)
#define CLKID_GPU_P1_MUX (CLKID_GPU_BASE + 4)
#define CLKID_GPU_P1_DIV (CLKID_GPU_BASE + 5)
#define CLKID_GPU_P1_GATE (CLKID_GPU_BASE + 6)
#define CLKID_GPU_P1_COMP (CLKID_GPU_BASE + 7)
#define CLKID_GPU_MUX (CLKID_GPU_BASE + 8)
#define CLKID_MEDIA_BASE (CLKID_GPU_BASE + 9)
#define CLKID_VPU_P0_MUX (CLKID_MEDIA_BASE + 0)
#define CLKID_VPU_P0_DIV (CLKID_MEDIA_BASE + 1)
#define CLKID_VPU_P0_GATE (CLKID_MEDIA_BASE + 2)
#define CLKID_VPU_P0_COMP (CLKID_MEDIA_BASE + 3)
#define CLKID_VPU_P1_MUX (CLKID_MEDIA_BASE + 4)
#define CLKID_VPU_P1_DIV (CLKID_MEDIA_BASE + 5)
#define CLKID_VPU_P1_GATE (CLKID_MEDIA_BASE + 6)
#define CLKID_VPU_P1_COMP (CLKID_MEDIA_BASE + 7)
#define CLKID_VPU_MUX (CLKID_MEDIA_BASE + 8)
#define CLKID_VAPB_P0_MUX (CLKID_MEDIA_BASE + 9)
#define CLKID_VAPB_P0_DIV (CLKID_MEDIA_BASE + 10)
#define CLKID_VAPB_P0_GATE (CLKID_MEDIA_BASE + 11)
#define CLKID_VAPB_P0_COMP (CLKID_MEDIA_BASE + 12)
#define CLKID_VAPB_P1_MUX (CLKID_MEDIA_BASE + 13)
#define CLKID_VAPB_P1_DIV (CLKID_MEDIA_BASE + 14)
#define CLKID_VAPB_P1_GATE (CLKID_MEDIA_BASE + 15)
#define CLKID_VAPB_P1_COMP (CLKID_MEDIA_BASE + 16)
#define CLKID_VAPB_MUX (CLKID_MEDIA_BASE + 17)
#define CLKID_GE2D_GATE (CLKID_MEDIA_BASE + 18)
#define CLKID_DSI_MEAS_MUX (CLKID_MEDIA_BASE + 19)
#define CLKID_DSI_MEAS_DIV (CLKID_MEDIA_BASE + 20)
#define CLKID_DSI_MEAS_GATE (CLKID_MEDIA_BASE + 21)
#define CLKID_DSI_MEAS_COMP (CLKID_MEDIA_BASE + 22)
#define CLKID_VPU_CLKB_TMP_COMP (CLKID_MEDIA_BASE + 23)
#define CLKID_VPU_CLKB_COMP (CLKID_MEDIA_BASE + 24)
#define CLKID_VDEC_P0_MUX (CLKID_MEDIA_BASE + 25)
#define CLKID_VDEC_P0_DIV (CLKID_MEDIA_BASE + 26)
#define CLKID_VDEC_P0_GATE (CLKID_MEDIA_BASE + 27)
#define CLKID_VDEC_P0_COMP (CLKID_MEDIA_BASE + 28)
#define CLKID_VDEC_P1_MUX (CLKID_MEDIA_BASE + 29)
#define CLKID_VDEC_P1_DIV (CLKID_MEDIA_BASE + 30)
#define CLKID_VDEC_P1_GATE (CLKID_MEDIA_BASE + 31)
#define CLKID_VDEC_P1_COMP (CLKID_MEDIA_BASE + 32)
#define CLKID_VDEC_MUX (CLKID_MEDIA_BASE + 33)
#define CLKID_HCODEC_P0_MUX (CLKID_MEDIA_BASE + 34)
#define CLKID_HCODEC_P0_DIV (CLKID_MEDIA_BASE + 35)
#define CLKID_HCODEC_P0_GATE (CLKID_MEDIA_BASE + 36)
#define CLKID_HCODEC_P0_COMP (CLKID_MEDIA_BASE + 37)
#define CLKID_HCODEC_P1_MUX (CLKID_MEDIA_BASE + 38)
#define CLKID_HCODEC_P1_DIV (CLKID_MEDIA_BASE + 39)
#define CLKID_HCODEC_P1_GATE (CLKID_MEDIA_BASE + 40)
#define CLKID_HCODEC_P1_COMP (CLKID_MEDIA_BASE + 41)
#define CLKID_HCODEC_MUX (CLKID_MEDIA_BASE + 42)
/*HEVCB_CLK*/
#define CLKID_HEVC_P0_MUX (CLKID_MEDIA_BASE + 43)
#define CLKID_HEVC_P0_DIV (CLKID_MEDIA_BASE + 44)
#define CLKID_HEVC_P0_GATE (CLKID_MEDIA_BASE + 45)
#define CLKID_HEVC_P0_COMP (CLKID_MEDIA_BASE + 46)
#define CLKID_HEVC_P1_MUX (CLKID_MEDIA_BASE + 47)
#define CLKID_HEVC_P1_DIV (CLKID_MEDIA_BASE + 48)
#define CLKID_HEVC_P1_GATE (CLKID_MEDIA_BASE + 49)
#define CLKID_HEVC_P1_COMP (CLKID_MEDIA_BASE + 50)
#define CLKID_HEVC_MUX (CLKID_MEDIA_BASE + 51)
/*HEVCF_CLK*/
#define CLKID_HEVCF_P0_MUX (CLKID_MEDIA_BASE + 52)
#define CLKID_HEVCF_P0_DIV (CLKID_MEDIA_BASE + 53)
#define CLKID_HEVCF_P0_GATE (CLKID_MEDIA_BASE + 54)
#define CLKID_HEVCF_P0_COMP (CLKID_MEDIA_BASE + 55)
#define CLKID_HEVCF_P1_MUX (CLKID_MEDIA_BASE + 56)
#define CLKID_HEVCF_P1_DIV (CLKID_MEDIA_BASE + 57)
#define CLKID_HEVCF_P1_GATE (CLKID_MEDIA_BASE + 58)
#define CLKID_HEVCF_P1_COMP (CLKID_MEDIA_BASE + 59)
#define CLKID_HEVCF_MUX (CLKID_MEDIA_BASE + 60)
#define CLKID_VPU_CLKC_P0_MUX (CLKID_MEDIA_BASE + 61)
#define CLKID_VPU_CLKC_P0_DIV (CLKID_MEDIA_BASE + 62)
#define CLKID_VPU_CLKC_P0_GATE (CLKID_MEDIA_BASE + 63)
#define CLKID_VPU_CLKC_P0_COMP (CLKID_MEDIA_BASE + 64)
#define CLKID_VPU_CLKC_P1_MUX (CLKID_MEDIA_BASE + 65)
#define CLKID_VPU_CLKC_P1_DIV (CLKID_MEDIA_BASE + 66)
#define CLKID_VPU_CLKC_P1_GATE (CLKID_MEDIA_BASE + 67)
#define CLKID_VPU_CLKC_P1_COMP (CLKID_MEDIA_BASE + 68)
#define CLKID_VPU_CLKC_MUX (CLKID_MEDIA_BASE + 69)
#define CLKID_BT656_MUX (CLKID_MEDIA_BASE + 70)
#define CLKID_BT656_DIV (CLKID_MEDIA_BASE + 71)
#define CLKID_BT656_GATE (CLKID_MEDIA_BASE + 72)
#define CLKID_BT656_COMP (CLKID_MEDIA_BASE + 73)
#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 74)
#define CLKID_SPICC0_MUX (CLKID_MISC_BASE + 0)
#define CLKID_SPICC0_DIV (CLKID_MISC_BASE + 1)
#define CLKID_SPICC0_GATE (CLKID_MISC_BASE + 2)
#define CLKID_SPICC0_COMP (CLKID_MISC_BASE + 3)
#define CLKID_SPICC1_MUX (CLKID_MISC_BASE + 4)
#define CLKID_SPICC1_DIV (CLKID_MISC_BASE + 5)
#define CLKID_SPICC1_GATE (CLKID_MISC_BASE + 6)
#define CLKID_SPICC1_COMP (CLKID_MISC_BASE + 7)
#define CLKID_TS_COMP (CLKID_MISC_BASE + 8)
/*gpio 12M/24M */
#define CLKID_24M (CLKID_MISC_BASE + 9)
#define CLKID_12M_DIV (CLKID_MISC_BASE + 10)
#define CLKID_12M_GATE (CLKID_MISC_BASE + 11)
/* gen clock */
#define CLKID_GEN_CLK_SEL (CLKID_MISC_BASE + 12)
#define CLKID_GEN_CLK_DIV (CLKID_MISC_BASE + 13)
#define CLKID_GEN_CLK (CLKID_MISC_BASE + 14)
/*G12B clk*/
#define CLKID_G12B_ADD_BASE (CLKID_MISC_BASE + 15)
#define CLKID_CPUB_FCLK_P (CLKID_G12B_ADD_BASE + 0)
#define CLKID_CPUB_CLK (CLKID_G12B_ADD_BASE + 1)
/*G12B gate*/
#define CLKID_CSI_DIG (CLKID_G12B_ADD_BASE + 2)
#define CLKID_VIPNANOQ (CLKID_G12B_ADD_BASE + 3)
#define CLKID_GDC (CLKID_G12B_ADD_BASE + 4)
#define CLKID_MIPI_ISP (CLKID_G12B_ADD_BASE + 5)
#define CLKID_CSI2_PHY1 (CLKID_G12B_ADD_BASE + 6)
#define CLKID_CSI2_PHY0 (CLKID_G12B_ADD_BASE + 7)
#define CLKID_GDC_CORE_CLK_COMP (CLKID_G12B_ADD_BASE + 8)
#define CLKID_GDC_AXI_CLK_COMP (CLKID_G12B_ADD_BASE + 9)
#define CLKID_VNANOQ_CORE_CLK_COMP (CLKID_G12B_ADD_BASE + 10)
#define CLKID_VNANOQ_AXI_CLK_COMP (CLKID_G12B_ADD_BASE + 11)
#define CLKID_VNANOQ_MUX (CLKID_G12B_ADD_BASE + 12)
#define CLKID_MIPI_ISP_CLK_COMP (CLKID_G12B_ADD_BASE + 13)
#define CLKID_MIPI_CSI_PHY_CLK0_COMP (CLKID_G12B_ADD_BASE + 14)
#define CLKID_MIPI_CSI_PHY_CLK1_COMP (CLKID_G12B_ADD_BASE + 15)
#define CLKID_MIPI_CSI_PHY_MUX (CLKID_G12B_ADD_BASE + 16)
#define CLKID_SYS1_PLL (CLKID_G12B_ADD_BASE + 17)
#define CLKID_SM1_ADD_BASE (CLKID_G12B_ADD_BASE + 18)
#define CLKID_GP1_PLL (CLKID_SM1_ADD_BASE + 0)
#define CLKID_DSU_PRE_SRC0 (CLKID_SM1_ADD_BASE + 1)
#define CLKID_DSU_PRE_SRC1 (CLKID_SM1_ADD_BASE + 2)
#define CLKID_DSU_CLK_DIV0 (CLKID_SM1_ADD_BASE + 3)
#define CLKID_DSU_CLK_DIV1 (CLKID_SM1_ADD_BASE + 4)
#define CLKID_DSU_PRE_MUX0 (CLKID_SM1_ADD_BASE + 5)
#define CLKID_DSU_PRE_MUX1 (CLKID_SM1_ADD_BASE + 6)
#define CLKID_DSU_PRE_POST_MUX (CLKID_SM1_ADD_BASE + 7)
#define CLKID_DSU_PRE_CLK (CLKID_SM1_ADD_BASE + 8)
#define CLKID_DSU_CLK (CLKID_SM1_ADD_BASE + 9)
#define CLKID_CSI_DIG_CLK (CLKID_SM1_ADD_BASE + 10)
#define CLKID_NNA_CLK (CLKID_SM1_ADD_BASE + 11)
#define CLKID_PARSER1_CLK (CLKID_SM1_ADD_BASE + 12)
#define CLKID_CSI_HOST_CLK (CLKID_SM1_ADD_BASE + 13)
#define CLKID_CSI_ADPAT_CLK (CLKID_SM1_ADD_BASE + 14)
#define CLKID_TEMP_SENSOR_CLK (CLKID_SM1_ADD_BASE + 15)
#define CLKID_CSI_PHY_CLK (CLKID_SM1_ADD_BASE + 16)
#define CLKID_MIPI_CSI_PHY_CLK_COMP (CLKID_SM1_ADD_BASE + 17)
#define CLKID_CSI_ADAPT_CLK_COMP (CLKID_SM1_ADD_BASE + 18)
#define CLKID_AO_BASE (CLKID_SM1_ADD_BASE + 19)
#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)
#define CLKID_SARADC_GATE (CLKID_AO_BASE + 3)
#define NR_CLKS (CLKID_AO_BASE + 4)
#define CLKID_END (MISC_BASE + 9)
#endif /* __G12A_CLKC_H */