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clk: vdec set 800M frequency [1/1]

Browse Source 
PD#SWPL-135101

Problem:
vdec set 800M frequency fail

Solution:
fix fclk_div2p5 configuration

Verify:
pxp

Change-Id: Iabb813b09b5059b06923781fcb49ab7074c035bb
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
This commit is contained in:
yiting.deng
2023-08-07 15:18:54 +08:00
committed by pengzhao.liu
parent 3d723b36dc
commit 586d413b41
1 changed files with 1 additions and 1 deletions
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drivers/clk/meson/s7.c
+1 -1
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@@ -696,7 +696,7 @@ MESON_CLK_FIXED_FACTOR(fclk_div5_div, 1, 5, &fixed_pll.hw, 0);
MESON_CLK_GATE_RO(fclk_div5, ANACTRL_FIXPLL_CTRL1, 28, 0, &fclk_div5_div.hw, 0);
MESON_CLK_FIXED_FACTOR(fclk_div7_div, 1, 7, &fixed_pll.hw, 0);
MESON_CLK_GATE_RO(fclk_div7, ANACTRL_FIXPLL_CTRL1, 29, 0, &fclk_div7_div.hw, 0);
MESON_CLK_FIXED_FACTOR(fclk_div2p5_div, 5, 2, &fixed_pll.hw, 0);
MESON_CLK_FIXED_FACTOR(fclk_div2p5_div, 2, 5, &fixed_pll.hw, 0);
MESON_CLK_GATE_RO(fclk_div2p5, ANACTRL_FIXPLL_CTRL0, 25, 0, &fclk_div2p5_div.hw, 0);
MESON_CLK_FIXED_FACTOR(fclk_clk50m_div, 1, 40, &fixed_pll.hw, 0);
MESON_CLK_GATE_RO(fclk_clk50m, ANACTRL_FIXPLL_CTRL1, 31, 0, &fclk_clk50m_div.hw, 0);