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g12a/g12b/sm1: update clock tree [1/1]

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PD#SWPL-107164

Problem:
1 sys_pll/sys1_pll does not support to 1512M
2 clkid is stored in multiple header files

Solution:
1 added frequency point support
2 clkid is placed under the same header file

Verify:
w400/ac200

Change-Id: I47d7f7c36b830285cfa4800ca0d90651629edb7e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
This commit is contained in:
Chuan Liu
2023-01-03 19:33:39 +08:00
committed by yao zhang1
parent 4a36611356
commit 6a4094dcf6
5 changed files with 128 additions and 153 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/clk/meson/g12a-aoclk.h
-19
View File
@@ -6,25 +6,6 @@
#ifndef __G12A_AOCLKC_H
#define __G12A_AOCLKC_H
/*
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
* It has now been decided to expose everything by default in the DT header:
* include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
* to expose, such as the internal muxes and dividers of composite clocks,
* will remain defined here.
*/
#define CLKID_AO_SAR_ADC_DIV 17
#define CLKID_AO_32K_PRE 20
#define CLKID_AO_32K_DIV 21
#define CLKID_AO_32K_SEL 22
#define CLKID_AO_CEC_PRE 24
#define CLKID_AO_CEC_DIV 25
#define CLKID_AO_CEC_SEL 26
#define NR_CLKS 29
#include <dt-bindings/clock/amlogic,g12a-aoclkc.h>
#include <dt-bindings/reset/g12a-aoclkc.h>
drivers/clk/meson/g12a.c
+5 -5
View File
@@ -86,7 +86,7 @@ static struct clk_regmap g12a_fixed_pll = {
};
static const struct pll_mult_range g12a_sys_pll_mult_range = {
.min = 128,
.min = 125,
.max = 250,
};
@@ -514,7 +514,7 @@ static struct clk_regmap g12a_cpu_clk_mux1_div = {
},
.hw.init = &(struct clk_init_data){
.name = "cpu_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops,
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk_premux1.hw
},
@@ -698,7 +698,7 @@ static struct clk_regmap g12b_cpub_clk_mux1_div = {
},
.hw.init = &(struct clk_init_data){
.name = "cpub_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops,
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12b_cpub_clk_premux1.hw
},
@@ -819,7 +819,7 @@ static struct clk_regmap sm1_dsu_clk_mux0_div = {
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn0_div",
.ops = &clk_regmap_divider_ro_ops,
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_premux0.hw
},
@@ -856,7 +856,7 @@ static struct clk_regmap sm1_dsu_clk_mux1_div = {
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops,
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_premux1.hw
},
drivers/clk/meson/g12a.h
-129
View File
@@ -124,135 +124,6 @@
#define HHI_SYS1_PLL_CNTL6 0x398
#define HHI_BT656_CLK_CNTL 0x3d4 /* 0xf5 offset in datasheet1 */
/*
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
* It has now been decided to expose everything by default in the DT header:
* include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
* to expose, such as the internal muxes and dividers of composite clocks,
* will remain defined here.
*/
#define CLKID_MPEG_SEL 8
#define CLKID_MPEG_DIV 9
#define CLKID_SD_EMMC_A_CLK0_SEL 63
#define CLKID_SD_EMMC_A_CLK0_DIV 64
#define CLKID_SD_EMMC_B_CLK0_SEL 65
#define CLKID_SD_EMMC_B_CLK0_DIV 66
#define CLKID_SD_EMMC_C_CLK0_SEL 67
#define CLKID_SD_EMMC_C_CLK0_DIV 68
#define CLKID_MPLL0_DIV 69
#define CLKID_MPLL1_DIV 70
#define CLKID_MPLL2_DIV 71
#define CLKID_MPLL3_DIV 72
#define CLKID_MPLL_PREDIV 73
#define CLKID_FCLK_DIV2_DIV 75
#define CLKID_FCLK_DIV3_DIV 76
#define CLKID_FCLK_DIV4_DIV 77
#define CLKID_FCLK_DIV5_DIV 78
#define CLKID_FCLK_DIV7_DIV 79
#define CLKID_FCLK_DIV2P5_DIV 100
#define CLKID_FIXED_PLL_DCO 101
#define CLKID_SYS_PLL_DCO 102
#define CLKID_GP0_PLL_DCO 103
#define CLKID_HIFI_PLL_DCO 104
#define CLKID_VPU_0_DIV 111
#define CLKID_VPU_1_DIV 114
#define CLKID_VAPB_0_DIV 118
#define CLKID_VAPB_1_DIV 121
#define CLKID_HDMI_PLL_DCO 125
#define CLKID_HDMI_PLL_OD 126
#define CLKID_HDMI_PLL_OD2 127
#define CLKID_VID_PLL_SEL 130
#define CLKID_VID_PLL_DIV 131
#define CLKID_VCLK_SEL 132
#define CLKID_VCLK2_SEL 133
#define CLKID_VCLK_INPUT 134
#define CLKID_VCLK2_INPUT 135
#define CLKID_VCLK_DIV 136
#define CLKID_VCLK2_DIV 137
#define CLKID_VCLK_DIV2_EN 140
#define CLKID_VCLK_DIV4_EN 141
#define CLKID_VCLK_DIV6_EN 142
#define CLKID_VCLK_DIV12_EN 143
#define CLKID_VCLK2_DIV2_EN 144
#define CLKID_VCLK2_DIV4_EN 145
#define CLKID_VCLK2_DIV6_EN 146
#define CLKID_VCLK2_DIV12_EN 147
#define CLKID_CTS_ENCI_SEL 158
#define CLKID_CTS_ENCP_SEL 159
#define CLKID_CTS_VDAC_SEL 160
#define CLKID_HDMI_TX_SEL 161
#define CLKID_HDMI_SEL 166
#define CLKID_HDMI_DIV 167
#define CLKID_MALI_0_DIV 170
#define CLKID_MALI_1_DIV 173
#define CLKID_MPLL_50M_DIV 176
#define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180
#define CLKID_CPU_CLK_DYN0_DIV 181
#define CLKID_CPU_CLK_DYN0 182
#define CLKID_CPU_CLK_DYN1_SEL 183
#define CLKID_CPU_CLK_DYN1_DIV 184
#define CLKID_CPU_CLK_DYN1 185
#define CLKID_CPU_CLK_DIV16_EN 188
#define CLKID_CPU_CLK_DIV16 189
#define CLKID_CPU_CLK_APB_DIV 190
#define CLKID_CPU_CLK_APB 191
#define CLKID_CPU_CLK_ATB_DIV 192
#define CLKID_CPU_CLK_ATB 193
#define CLKID_CPU_CLK_AXI_DIV 194
#define CLKID_CPU_CLK_AXI 195
#define CLKID_CPU_CLK_TRACE_DIV 196
#define CLKID_CPU_CLK_TRACE 197
#define CLKID_PCIE_PLL_DCO 198
#define CLKID_PCIE_PLL_DCO_DIV2 199
#define CLKID_PCIE_PLL_OD 200
#define CLKID_VDEC_1_SEL 202
#define CLKID_VDEC_1_DIV 203
#define CLKID_VDEC_HEVC_SEL 205
#define CLKID_VDEC_HEVC_DIV 206
#define CLKID_VDEC_HEVCF_SEL 208
#define CLKID_VDEC_HEVCF_DIV 209
#define CLKID_TS_DIV 211
#define CLKID_SYS1_PLL_DCO 213
#define CLKID_SYS1_PLL 214
#define CLKID_SYS1_PLL_DIV16_EN 215
#define CLKID_SYS1_PLL_DIV16 216
#define CLKID_CPUB_CLK_DYN0_SEL 217
#define CLKID_CPUB_CLK_DYN0_DIV 218
#define CLKID_CPUB_CLK_DYN0 219
#define CLKID_CPUB_CLK_DYN1_SEL 220
#define CLKID_CPUB_CLK_DYN1_DIV 221
#define CLKID_CPUB_CLK_DYN1 222
#define CLKID_CPUB_CLK_DYN 223
#define CLKID_CPUB_CLK_DIV16_EN 225
#define CLKID_CPUB_CLK_DIV16 226
#define CLKID_CPUB_CLK_DIV2 227
#define CLKID_CPUB_CLK_DIV3 228
#define CLKID_CPUB_CLK_DIV4 229
#define CLKID_CPUB_CLK_DIV5 230
#define CLKID_CPUB_CLK_DIV6 231
#define CLKID_CPUB_CLK_DIV7 232
#define CLKID_CPUB_CLK_DIV8 233
#define CLKID_CPUB_CLK_APB_SEL 234
#define CLKID_CPUB_CLK_APB 235
#define CLKID_CPUB_CLK_ATB_SEL 236
#define CLKID_CPUB_CLK_ATB 237
#define CLKID_CPUB_CLK_AXI_SEL 238
#define CLKID_CPUB_CLK_AXI 239
#define CLKID_CPUB_CLK_TRACE_SEL 240
#define CLKID_CPUB_CLK_TRACE 241
#define CLKID_GP1_PLL_DCO 242
#define CLKID_DSU_CLK_DYN0_SEL 244
#define CLKID_DSU_CLK_DYN0_DIV 245
#define CLKID_DSU_CLK_DYN0 246
#define CLKID_DSU_CLK_DYN1_SEL 247
#define CLKID_DSU_CLK_DYN1_DIV 248
#define CLKID_DSU_CLK_DYN1 249
#define CLKID_DSU_CLK_DYN 250
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/amlogic,g12a-clkc.h>
include/dt-bindings/clock/amlogic,g12a-aoclkc.h
+9
View File
@@ -23,10 +23,19 @@
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_SEL 16
#define CLKID_AO_SAR_ADC_DIV 17
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_CTS_OSCIN 19
#define CLKID_AO_32K_PRE 20
#define CLKID_AO_32K_DIV 21
#define CLKID_AO_32K_SEL 22
#define CLKID_AO_32K 23
#define CLKID_AO_CEC_PRE 24
#define CLKID_AO_CEC_DIV 25
#define CLKID_AO_CEC_SEL 26
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28
#define NR_CLKS 29
#endif
include/dt-bindings/clock/amlogic,g12a-clkc.h
+114
View File
@@ -14,6 +14,8 @@
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_MPEG_SEL 8
#define CLKID_MPEG_DIV 9
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
@@ -73,7 +75,17 @@
#define CLKID_SD_EMMC_B_CLK0_DIV 66
#define CLKID_SD_EMMC_C_CLK0_SEL 67
#define CLKID_SD_EMMC_C_CLK0_DIV 68
#define CLKID_MPLL0_DIV 69
#define CLKID_MPLL1_DIV 70
#define CLKID_MPLL2_DIV 71
#define CLKID_MPLL3_DIV 72
#define CLKID_MPLL_PREDIV 73
#define CLKID_HIFI_PLL 74
#define CLKID_FCLK_DIV2_DIV 75
#define CLKID_FCLK_DIV3_DIV 76
#define CLKID_FCLK_DIV4_DIV 77
#define CLKID_FCLK_DIV5_DIV 78
#define CLKID_FCLK_DIV7_DIV 79
#define CLKID_VCLK2_VENCI0 80
#define CLKID_VCLK2_VENCI1 81
#define CLKID_VCLK2_VENCP0 82
@@ -94,26 +106,54 @@
#define CLKID_VCLK2_VENCL 97
#define CLKID_VCLK2_OTHER1 98
#define CLKID_FCLK_DIV2P5 99
#define CLKID_FCLK_DIV2P5_DIV 100
#define CLKID_FIXED_PLL_DCO 101
#define CLKID_SYS_PLL_DCO 102
#define CLKID_GP0_PLL_DCO 103
#define CLKID_HIFI_PLL_DCO 104
#define CLKID_DMA 105
#define CLKID_EFUSE 106
#define CLKID_ROM_BOOT 107
#define CLKID_RESET_SEC 108
#define CLKID_SEC_AHB_APB3 109
#define CLKID_VPU_0_SEL 110
#define CLKID_VPU_0_DIV 111
#define CLKID_VPU_0 112
#define CLKID_VPU_1_SEL 113
#define CLKID_VPU_1_DIV 114
#define CLKID_VPU_1 115
#define CLKID_VPU 116
#define CLKID_VAPB_0_SEL 117
#define CLKID_VAPB_0_DIV 118
#define CLKID_VAPB_0 119
#define CLKID_VAPB_1_SEL 120
#define CLKID_VAPB_1_DIV 121
#define CLKID_VAPB_1 122
#define CLKID_VAPB_SEL 123
#define CLKID_VAPB 124
#define CLKID_HDMI_PLL_DCO 125
#define CLKID_HDMI_PLL_OD 126
#define CLKID_HDMI_PLL_OD2 127
#define CLKID_HDMI_PLL 128
#define CLKID_VID_PLL 129
#define CLKID_VID_PLL_SEL 130
#define CLKID_VID_PLL_DIV 131
#define CLKID_VCLK_SEL 132
#define CLKID_VCLK2_SEL 133
#define CLKID_VCLK_INPUT 134
#define CLKID_VCLK2_INPUT 135
#define CLKID_VCLK_DIV 136
#define CLKID_VCLK2_DIV 137
#define CLKID_VCLK 138
#define CLKID_VCLK2 139
#define CLKID_VCLK_DIV2_EN 140
#define CLKID_VCLK_DIV4_EN 141
#define CLKID_VCLK_DIV6_EN 142
#define CLKID_VCLK_DIV12_EN 143
#define CLKID_VCLK2_DIV2_EN 144
#define CLKID_VCLK2_DIV4_EN 145
#define CLKID_VCLK2_DIV6_EN 146
#define CLKID_VCLK2_DIV12_EN 147
#define CLKID_VCLK_DIV1 148
#define CLKID_VCLK_DIV2 149
#define CLKID_VCLK_DIV4 150
@@ -124,26 +164,99 @@
#define CLKID_VCLK2_DIV4 155
#define CLKID_VCLK2_DIV6 156
#define CLKID_VCLK2_DIV12 157
#define CLKID_CTS_ENCI_SEL 158
#define CLKID_CTS_ENCP_SEL 159
#define CLKID_CTS_VDAC_SEL 160
#define CLKID_HDMI_TX_SEL 161
#define CLKID_CTS_ENCI 162
#define CLKID_CTS_ENCP 163
#define CLKID_CTS_VDAC 164
#define CLKID_HDMI_TX 165
#define CLKID_HDMI_SEL 166
#define CLKID_HDMI_DIV 167
#define CLKID_HDMI 168
#define CLKID_MALI_0_SEL 169
#define CLKID_MALI_0_DIV 170
#define CLKID_MALI_0 171
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1_DIV 173
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_50M_DIV 176
#define CLKID_MPLL_50M 177
#define CLKID_SYS_PLL_DIV16_EN 178
#define CLKID_SYS_PLL_DIV16 179
#define CLKID_CPU_CLK_DYN0_SEL 180
#define CLKID_CPU_CLK_DYN0_DIV 181
#define CLKID_CPU_CLK_DYN0 182
#define CLKID_CPU_CLK_DYN1_SEL 183
#define CLKID_CPU_CLK_DYN1_DIV 184
#define CLKID_CPU_CLK_DYN1 185
#define CLKID_CPU_CLK_DYN 186
#define CLKID_CPU_CLK 187
#define CLKID_CPU_CLK_DIV16_EN 188
#define CLKID_CPU_CLK_DIV16 189
#define CLKID_CPU_CLK_APB_DIV 190
#define CLKID_CPU_CLK_APB 191
#define CLKID_CPU_CLK_ATB_DIV 192
#define CLKID_CPU_CLK_ATB 193
#define CLKID_CPU_CLK_AXI_DIV 194
#define CLKID_CPU_CLK_AXI 195
#define CLKID_CPU_CLK_TRACE_DIV 196
#define CLKID_CPU_CLK_TRACE 197
#define CLKID_PCIE_PLL_DCO 198
#define CLKID_PCIE_PLL_DCO_DIV2 199
#define CLKID_PCIE_PLL_OD 200
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1_SEL 202
#define CLKID_VDEC_1_DIV 203
#define CLKID_VDEC_1 204
#define CLKID_VDEC_HEVC_SEL 205
#define CLKID_VDEC_HEVC_DIV 206
#define CLKID_VDEC_HEVC 207
#define CLKID_VDEC_HEVCF_SEL 208
#define CLKID_VDEC_HEVCF_DIV 209
#define CLKID_VDEC_HEVCF 210
#define CLKID_TS_DIV 211
#define CLKID_TS 212
#define CLKID_SYS1_PLL_DCO 213
#define CLKID_SYS1_PLL 214
#define CLKID_SYS1_PLL_DIV16_EN 215
#define CLKID_SYS1_PLL_DIV16 216
#define CLKID_CPUB_CLK_DYN0_SEL 217
#define CLKID_CPUB_CLK_DYN0_DIV 218
#define CLKID_CPUB_CLK_DYN0 219
#define CLKID_CPUB_CLK_DYN1_SEL 220
#define CLKID_CPUB_CLK_DYN1_DIV 221
#define CLKID_CPUB_CLK_DYN1 222
#define CLKID_CPUB_CLK_DYN 223
#define CLKID_CPUB_CLK 224
#define CLKID_CPUB_CLK_DIV16_EN 225
#define CLKID_CPUB_CLK_DIV16 226
#define CLKID_CPUB_CLK_DIV2 227
#define CLKID_CPUB_CLK_DIV3 228
#define CLKID_CPUB_CLK_DIV4 229
#define CLKID_CPUB_CLK_DIV5 230
#define CLKID_CPUB_CLK_DIV6 231
#define CLKID_CPUB_CLK_DIV7 232
#define CLKID_CPUB_CLK_DIV8 233
#define CLKID_CPUB_CLK_APB_SEL 234
#define CLKID_CPUB_CLK_APB 235
#define CLKID_CPUB_CLK_ATB_SEL 236
#define CLKID_CPUB_CLK_ATB 237
#define CLKID_CPUB_CLK_AXI_SEL 238
#define CLKID_CPUB_CLK_AXI 239
#define CLKID_CPUB_CLK_TRACE_SEL 240
#define CLKID_CPUB_CLK_TRACE 241
#define CLKID_GP1_PLL_DCO 242
#define CLKID_GP1_PLL 243
#define CLKID_DSU_CLK_DYN0_SEL 244
#define CLKID_DSU_CLK_DYN0_DIV 245
#define CLKID_DSU_CLK_DYN0 246
#define CLKID_DSU_CLK_DYN1_SEL 247
#define CLKID_DSU_CLK_DYN1_DIV 248
#define CLKID_DSU_CLK_DYN1 249
#define CLKID_DSU_CLK_DYN 250
#define CLKID_DSU_CLK_FINAL 251
#define CLKID_DSU_CLK 252
#define CLKID_CPU1_CLK 253
@@ -151,6 +264,7 @@
#define CLKID_CPU3_CLK 255
#define CLKID_PCIE_HCSL 256
#define CLKID_PCIE_BGP 257
/* Media clocks */
#define MEDIA_BASE (258 + 1)
#define CLKID_DSI_MEAS_MUX (MEDIA_BASE + 0)