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lcd: tcon: update tcon init flow [2/2]

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PD#SWPL-161412

Problem:
tcon init flow need update for system continuous vsync

Solution:
on/off pre_proc_clk instead of encl_video_en register

Verify:
ay301

Change-Id: I9917662e5e06ac0cf06a2325c3d1eaf077bab038
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2024-03-05 12:00:55 +08:00
committed by gerrit autosubmit
parent b015cebfc9
commit 6bd80dd7d8
4 changed files with 28 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vout/lcd/lcd_common.h
+2 -1
View File
@@ -61,7 +61,8 @@
/* 20240222: update custom control support*/
/* 20240226: add tcon init_table pre_proc*/
/* 20240307: update swpdf support*/
#define LCD_DRV_VERSION "20240307"
/* 20240319: add tcon pre_proc_clk_en control*/
#define LCD_DRV_VERSION "20240319"
static inline unsigned char __p_to_u8(void *p)
{
drivers/media/vout/lcd/lcd_tcon.c
+8 -6
View File
@@ -1126,6 +1126,8 @@ void lcd_tcon_disable(struct aml_lcd_drv_s *pdrv)
if (lcd_tcon_conf->tcon_disable)
lcd_tcon_conf->tcon_disable(pdrv);
if (lcd_tcon_conf->tcon_global_reset)
lcd_tcon_conf->tcon_global_reset(pdrv);
}
void lcd_tcon_dbg_check(struct aml_lcd_drv_s *pdrv, struct lcd_detail_timing_s *ptiming)
@@ -3552,8 +3554,8 @@ static struct lcd_tcon_config_s tcon_data_t3 = {
.tcon_axi_mem_secure = lcd_tcon_axi_mem_secure_t3,
.tcon_init_table_pre_proc = lcd_tcon_init_table_pre_proc,
.tcon_global_reset = lcd_tcon_global_reset_t3,
.tcon_enable = lcd_tcon_enable_t3,
.tcon_disable = lcd_tcon_disable_t3,
.tcon_enable = lcd_tcon_enable_t5,
.tcon_disable = lcd_tcon_disable_t5,
.tcon_reload = lcd_tcon_reload_t3,
.tcon_reload_pre = lcd_tcon_reload_pre_t3,
.lut_dma_update = NULL,
@@ -3602,8 +3604,8 @@ static struct lcd_tcon_config_s tcon_data_t5m = {
.tcon_axi_mem_secure = lcd_tcon_axi_mem_secure_t3,
.tcon_init_table_pre_proc = lcd_tcon_init_table_pre_proc,
.tcon_global_reset = lcd_tcon_global_reset_t3,
.tcon_enable = lcd_tcon_enable_t3,
.tcon_disable = lcd_tcon_disable_t3,
.tcon_enable = lcd_tcon_enable_t5,
.tcon_disable = lcd_tcon_disable_t5,
.tcon_reload = lcd_tcon_reload_t3,
.tcon_reload_pre = lcd_tcon_reload_pre_t3,
.lut_dma_update = lcd_tcon_lut_dma_update,
@@ -3704,8 +3706,8 @@ static struct lcd_tcon_config_s tcon_data_t3x = {
.tcon_axi_mem_secure = lcd_tcon_axi_mem_secure_t3,
.tcon_init_table_pre_proc = lcd_tcon_init_table_pre_proc,
.tcon_global_reset = lcd_tcon_global_reset_t3x,
.tcon_enable = lcd_tcon_enable_t3,
.tcon_disable = lcd_tcon_disable_t3x,
.tcon_enable = lcd_tcon_enable_t5,
.tcon_disable = lcd_tcon_disable_t5,
.tcon_reload = lcd_tcon_reload_t3,
.tcon_reload_pre = lcd_tcon_reload_pre_t3,
.lut_dma_update = NULL,
drivers/media/vout/lcd/lcd_tcon.h
-3
View File
@@ -302,9 +302,6 @@ int lcd_tcon_enable_tl1(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_disable_tl1(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_enable_t5(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_disable_t5(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_enable_t3(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_disable_t3(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_disable_t3x(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_reload_t3(struct aml_lcd_drv_s *pdrv);
int lcd_tcon_reload_pre_t3(struct aml_lcd_drv_s *pdrv);
drivers/media/vout/lcd/lcd_tcon_hw.c
+18 -99
View File
@@ -215,6 +215,9 @@ void lcd_tcon_init_table_pre_proc(unsigned char *table)
return;
table32 = (unsigned int *)table;
//pre_proc_clk disable
table32[0x207] &= ~(1 << 4);
//od ddrif disable
table32[0x263] &= ~(1 << 31);
//demura ddrif disable
@@ -1497,7 +1500,9 @@ int lcd_tcon_enable_t5(struct aml_lcd_drv_s *pdrv)
lcd_tcon_bin_load(pdrv);
}
lcd_venc_enable(pdrv, 0);
//don't disable encl for system continuous vsync,
// just disable tcon pre_proc_clk in tcon bin
//lcd_venc_enable(pdrv, 0);
/* step 1: tcon top */
lcd_tcon_top_set_t5(pdrv);
@@ -1522,7 +1527,8 @@ int lcd_tcon_enable_t5(struct aml_lcd_drv_s *pdrv)
/* step 5: tcon_intr_mask */
lcd_tcon_write(pdrv, TCON_INTR_MASKN, TCON_INTR_MASKN_VAL);
lcd_venc_enable(pdrv, 1);
//lcd_venc_enable(pdrv, 1);
lcd_tcon_setb(pdrv, 0x207, 1, 4, 1);//enable pre_proc_clk
return 0;
}
@@ -1544,9 +1550,11 @@ int lcd_tcon_reload_pre_t3(struct aml_lcd_drv_s *pdrv)
lcd_tcon_setb(pdrv, 0x26c, 0, 8, 1);
/* disable demura ddr_if */
lcd_tcon_setb(pdrv, 0x1a3, 0, 31, 1);
mdelay(20);
lcd_delay_ms(30);
//venc off
lcd_venc_enable(pdrv, 0);
//lcd_venc_enable(pdrv, 0);
lcd_tcon_setb(pdrv, 0x207, 0, 4, 1);//disable pre_proc_clk
if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("%s: read tcon reg_width: %d, goa:0x %x\n",
@@ -1576,11 +1584,14 @@ int lcd_tcon_reload_t3(struct aml_lcd_drv_s *pdrv)
}
}
//venc on
lcd_venc_enable(pdrv, 1);
//lcd_venc_enable(pdrv, 1);
local_time[1] = sched_clock();
if (mm_table->version)
lcd_tcon_data_set(pdrv, mm_table);
lcd_tcon_setb(pdrv, 0x207, 1, 4, 1);//enable pre_proc_clk
local_time[2] = sched_clock();
pdrv->config.cus_ctrl.reg_set_time = local_time[1] - local_time[0];
pdrv->config.cus_ctrl.data_set_time = local_time[2] - local_time[1];
@@ -1588,55 +1599,6 @@ int lcd_tcon_reload_t3(struct aml_lcd_drv_s *pdrv)
return 0;
}
int lcd_tcon_enable_t3(struct aml_lcd_drv_s *pdrv)
{
struct lcd_tcon_config_s *tcon_conf = get_lcd_tcon_config();
struct tcon_mem_map_table_s *mm_table = get_lcd_tcon_mm_table();
struct lcd_tcon_local_cfg_s *local_cfg = get_lcd_tcon_local_cfg();
int ret;
ret = lcd_tcon_valid_check();
if (ret)
return -1;
if (!tcon_conf || !mm_table || !local_cfg)
return -1;
if (mm_table->init_load == 0) {
if (mm_table->tcon_data_flag == 0)
lcd_tcon_bin_load(pdrv);
}
lcd_venc_enable(pdrv, 0);
/* step 1: tcon top */
lcd_tcon_top_set_t5(pdrv);
/* step 2: tcon_core_reg_update */
if (mm_table->core_reg_header) {
if (mm_table->core_reg_header->block_ctrl == 0) {
local_cfg->cur_core_reg_table = mm_table->core_reg_table;
lcd_tcon_core_reg_set(pdrv, tcon_conf,
mm_table, mm_table->core_reg_table);
}
}
/* step 3: tcon data set */
if (mm_table->version)
lcd_tcon_data_set(pdrv, mm_table);
/* step 4: tcon_top_output_set */
lcd_tcon_write(pdrv, TCON_OUT_CH_SEL0, 0x76543210);
lcd_tcon_write(pdrv, TCON_OUT_CH_SEL1, 0xba98);
/* step 5: tcon_intr_mask */
lcd_tcon_write(pdrv, TCON_INTR_MASKN, TCON_INTR_MASKN_VAL);
lcd_venc_enable(pdrv, 1);
return 0;
}
int lcd_tcon_disable_t5(struct aml_lcd_drv_s *pdrv)
{
/* disable unit(reg_func_enable) timing signal */
@@ -1654,51 +1616,8 @@ int lcd_tcon_disable_t5(struct aml_lcd_drv_s *pdrv)
/* top reset */
lcd_tcon_write(pdrv, TCON_RST_CTRL, 0x003f);
lcd_tcon_global_reset_t5(pdrv);
return 0;
}
int lcd_tcon_disable_t3(struct aml_lcd_drv_s *pdrv)
{
/* disable unit(reg_func_enable) timing signal */
lcd_tcon_write(pdrv, 0x30e, 0);
/* disable tcon intr */
lcd_tcon_write(pdrv, TCON_INTR_MASKN, 0);
/* disable od ddr_if */
lcd_tcon_setb(pdrv, 0x263, 0, 31, 1);
/* disable demura ddr_if */
lcd_tcon_setb(pdrv, 0x1a3, 0, 31, 1);
lcd_delay_ms(100);
/* top reset */
lcd_tcon_write(pdrv, TCON_RST_CTRL, 0x003f);
lcd_tcon_global_reset_t3(pdrv);
return 0;
}
int lcd_tcon_disable_t3x(struct aml_lcd_drv_s *pdrv)
{
/* disable unit(reg_func_enable) timing signal */
lcd_tcon_write(pdrv, 0x30e, 0);
/* disable tcon intr */
lcd_tcon_write(pdrv, TCON_INTR_MASKN, 0);
/* disable od ddr_if */
lcd_tcon_setb(pdrv, 0x263, 0, 31, 1);
/* disable demura ddr_if */
lcd_tcon_setb(pdrv, 0x1a3, 0, 31, 1);
lcd_delay_ms(100);
/* top reset */
lcd_tcon_write(pdrv, TCON_RST_CTRL, 0x003f);
lcd_tcon_global_reset_t3x(pdrv);
//move to tcon_disable api for common flow
//lcd_tcon_global_reset_t5(pdrv);
return 0;
}