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https://github.com/hardkernel/kernel_common_drivers.git
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adc: adjust adc clk config [1/1]
PD#SWPL-130758 Problem: adc clk config process has problem Solution: adjust adc clk config Verify: s4d Change-Id: I6f561a4be20c0c9243736de08d3e6883c22129e7 Signed-off-by: qiang.liu <qiang.liu@amlogic.com>
This commit is contained in:
qiang.liu
committed by
gerrit autosubmit
gerrit autosubmit
parent
9da4c411b7
commit
7b25efcf74
+31
-17
@@ -759,9 +759,6 @@ void adc_set_ddemod_default(struct dfe_adcpll_para *adcpll_para)
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if (!probe_finish)
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return;
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if (devp->print_en & ADC_DBG_EN)
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pr_info("%s: delsys:%#x id:%#x\n", __func__, delsys, devp->plat_data->chip_id);
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if (!adcpll_para) {
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pr_err("%s: adcpll_para is null!\n", __func__);
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return;
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@@ -769,6 +766,9 @@ void adc_set_ddemod_default(struct dfe_adcpll_para *adcpll_para)
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delsys = adcpll_para->delsys;
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mode = adcpll_para->mode;
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if (devp->print_en & ADC_DBG_EN)
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pr_info("%s: delsys:%#x id:%#x\n", __func__, delsys, devp->plat_data->chip_id);
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#ifndef CONFIG_AMLOGIC_REMOVE_OLD
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if (is_meson_txl_cpu() || is_meson_txlx_cpu() ||
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is_meson_gxlx_cpu()) {
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@@ -958,16 +958,17 @@ static void adc_set_dtvdemod_dpll_by_clk(struct tvin_adc_dev *devp,
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if (p_dtv_para->delsys == SYS_DVBC_ANNEX_A &&
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(p_dtv_para->mode & 0xff) == 2) {
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adc_wr_hiu(pll_addr->adc_pll_cntl_0 + reg_offset, 0x01050480);
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adc_wr_hiu(pll_addr->adc_pll_cntl_0 + reg_offset, 0x31050480);
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adc_wr_hiu(pll_addr->adc_pll_cntl_1 + reg_offset, 0x04000000);
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adc_wr_hiu(pll_addr->adc_pll_cntl_2 + reg_offset, 0x0);
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adc_wr_hiu(pll_addr->adc_pll_cntl_3 + reg_offset, 0x48681f00);
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adc_wr_hiu(pll_addr->adc_pll_cntl_4 + reg_offset, 0x33771291);
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adc_wr_hiu(pll_addr->adc_pll_cntl_5 + reg_offset, 0x3927a000);
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adc_wr_hiu(pll_addr->adc_pll_cntl_6 + reg_offset, 0x56540000);
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adc_wr_hiu(pll_addr->adc_pll_cntl_0 + reg_offset, 0x31050480);
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adc_wr_hiu(pll_addr->adc_pll_cntl_0 + reg_offset, 0x11050480);
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} else {
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adc_wr_hiu(pll_addr->adc_pll_cntl_0 + reg_offset, 0x0105047d);
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adc_wr_hiu(pll_addr->adc_pll_cntl_0 + reg_offset, 0x3105047d);
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//adc_wr_hiu(HHI_ADC_PLL_CNTL0_TL1 + reg_offset, 0x312004e0);
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adc_wr_hiu(pll_addr->adc_pll_cntl_1 + reg_offset, 0x03c00000);
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@@ -1175,6 +1176,7 @@ int adc_set_pll_cntl(bool on, enum adc_sel module_sel, void *p_para)
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if (devp->print_en & ADC_DBG_EN)
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pr_info("%s clk:%d delsys:%#x\n",
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__func__, p_dtv_para->adc_clk, p_dtv_para->delsys);
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devp->delsys = p_dtv_para->delsys;
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if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
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do {
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@@ -1364,27 +1366,39 @@ EXPORT_SYMBOL(adc_get_status);
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static void adc_pll_down(void)
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{
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int chip_id;
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unsigned int reg_offset;
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struct adc_reg_addr *adc_addr;
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struct adc_pll_reg_addr *pll_addr;
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if (!probe_finish || !adc_devp)
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return;
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struct adc_pll_reg_addr *pll_addr = &adc_devp->plat_data->pll_addr;
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struct adc_reg_addr *adc_addr = &adc_devp->plat_data->adc_addr;
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pr_info("adc: %s\n", __func__);
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pll_addr = &adc_devp->plat_data->pll_addr;
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adc_addr = &adc_devp->plat_data->adc_addr;
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chip_id = adc_devp->plat_data->chip_id;
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pr_info("adc: %s chid:%d\n", __func__, chip_id);
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if (chip_id == ADC_CHIP_S4 || chip_id == ADC_CHIP_S4D)
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reg_offset = 0x10;
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else
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reg_offset = 0;
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mutex_lock(&adc_devp->pll_mutex);
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if (!adc_devp->pll_flg && is_meson_tl1_cpu() &&
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adc_rd_hiu_bits(pll_addr->adc_pll_cntl_0, 28, 1)) {
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0, 0, 28, 1);
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adc_rd_hiu_bits(pll_addr->adc_pll_cntl_0 + reg_offset, 28, 1)) {
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0 + reg_offset, 0, 28, 1);
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}
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if (!adc_devp->pll_flg && adc_devp->plat_data->chip_id >= ADC_CHIP_T5) {
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adc_wr_hiu_bits(adc_addr->vdac_cntl_1, 0, 7, 1);
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adc_wr_hiu_bits(adc_addr->dadc_cntl_3, 0, 0, 2);
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0, 0, 28, 1);
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0 + reg_offset, 0, 28, 1);
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if (adc_devp->plat_data->is_tv_chip)
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adc_wr_hiu_bits(adc_addr->s2_dadc_cntl_2, 0, 8, 1);
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0, 1, 29, 1);
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0, 0, 29, 1);
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0 + reg_offset, 1, 29, 1);
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adc_wr_hiu_bits(pll_addr->adc_pll_cntl_0 + reg_offset, 0, 29, 1);
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}
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if (adc_devp->plat_data->is_tv_chip) {
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@@ -1461,9 +1475,9 @@ static void adc_dump_regs(void)
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pr_info("chip_id=0x%x is_tv=0x%x\n",
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chip_id, adc_devp->plat_data->is_tv_chip);
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pr_info("pll_flag=0x%x filter_flg=0x%x print_en=0x%x\n",
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pr_info("pll_flag=0x%x filter_flg=0x%x delsys:%d print_en=0x%x\n",
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adc_devp->pll_flg, adc_devp->filter_flg,
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adc_devp->print_en);
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adc_devp->delsys, adc_devp->print_en);
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if (chip_id == ADC_CHIP_S4 || chip_id == ADC_CHIP_S4D) {
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reg_offset = 0x10;
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@@ -1607,13 +1621,13 @@ static ssize_t adc_store(struct device *dev, struct device_attribute *attr,
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if (tmp_val) {
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p_dtv_para.delsys = SYS_DVBT;
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adc_set_filter_ctrl(true, FILTER_DTV_DEMOD, NULL);
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adc_set_pll_cntl(true, ADC_DTV_DEMOD, &p_dtv_para);
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adc_set_ddemod_default(&p_dtv_para);
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adc_set_pll_cntl(true, ADC_DTV_DEMOD, &p_dtv_para);
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} else {
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p_dtv_para.delsys = SYS_DVBS;
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adc_set_filter_ctrl(true, FILTER_DTV_DEMOD, NULL);
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adc_set_pll_cntl(true, ADC_DTV_DEMOD, &p_dtv_para);
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adc_set_ddemod_default(&p_dtv_para);
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adc_set_pll_cntl(true, ADC_DTV_DEMOD, &p_dtv_para);
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}
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} else {
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p_dtv_para.delsys = SYS_DVBT;
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@@ -1631,8 +1645,8 @@ static ssize_t adc_store(struct device *dev, struct device_attribute *attr,
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p_dtv_para.delsys = SYS_DVBC_ANNEX_A;
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p_dtv_para.adc_clk = ADC_CLK_24M;
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adc_set_filter_ctrl(true, FILTER_DTV_DEMOD, NULL);
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adc_set_pll_cntl(true, ADC_DTV_DEMOD, &p_dtv_para);
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adc_set_ddemod_default(&p_dtv_para);
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adc_set_pll_cntl(true, ADC_DTV_DEMOD, &p_dtv_para);
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} else {
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p_dtv_para.delsys = SYS_DVBC_ANNEX_A;
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adc_set_filter_ctrl(false, FILTER_DTV_DEMOD, NULL);
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@@ -16,7 +16,8 @@
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/* 20230331: change atv_demod_afc_do_work status judge */
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/* 20230615: solved demod not adc clock will crash */
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/* 20230705: change be311 config value */
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#define ADC_VER "20230705:change be311 config value"
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/* 20231114: S4D adjust adc clk config */
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#define ADC_VER "20231114: S4D adjust adc clk config"
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#define ADC_CLK_24M 24000
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#define ADC_CLK_25M 25000
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@@ -206,6 +207,7 @@ struct tvin_adc_dev {
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unsigned int pll_flg;
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unsigned int filter_flg;
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unsigned int print_en;
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enum fe_delivery_system delsys;
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struct adc_reg_phy phy_addr[MAP_ADDR_NUM];
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void __iomem *vir_addr[MAP_ADDR_NUM];
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};
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