video: add video support for s7 [1/1]

PD#SWPL-135794

Problem:
s7 video bringup

Solution:
complete it

Verify:
ptm

Change-Id: Ie00823bdc5cb95807c3ed1e54bfa2fa37be6a91c
Signed-off-by: yuhua.lin <yuhua.lin@amlogic.com>
Signed-off-by: pengzhao.liu <pengzhao.liu@amlogic.com>
This commit is contained in:
pengzhao.liu
2023-10-18 17:54:07 +08:00
committed by Luan Yuan
parent 8cf891198d
commit 7be9727f10
4 changed files with 81 additions and 4 deletions
+7 -2
View File
@@ -2062,13 +2062,18 @@
};
meson-amvideom {
compatible = "amlogic, amvideom-s4";
compatible = "amlogic, amvideom-s7";
dev_name = "amvideom";
status = "disabled";
status = "okay";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "vsync";
};
lut_dma:lut_dma {
compatible = "amlogic, meson-s5, lut_dma";
status = "okay";
};
video_composer {
compatible = "amlogic, video_composer";
dev_name = "video_composer";
+64
View File
@@ -14461,6 +14461,57 @@ static struct amvideo_device_data_s amvideo_s1a = {
};
#endif
static struct amvideo_device_data_s amvideo_s7 = {
.cpu_type = MESON_CPU_MAJOR_ID_S7_,
.sr_reg_offt = 0x1e00,
.sr_reg_offt2 = 0x1f80,
.layer_support[0] = 1,
.layer_support[1] = 1,
.layer_support[2] = 0,
.afbc_support[0] = 1,
.afbc_support[1] = 1,
.afbc_support[2] = 0,
.pps_support[0] = 1,
.pps_support[1] = 1,
.pps_support[2] = 0,
.alpha_support[0] = 1,
.alpha_support[1] = 1,
.alpha_support[2] = 0,
.dv_support = 0,
.sr0_support = 1,
.sr1_support = 0,
.core_v_disable_width_max[0] = 4096,
.core_v_disable_width_max[1] = 4096,
.core_v_enable_width_max[0] = 2048,
.core_v_enable_width_max[1] = 2048,
.supscl_path = CORE0_BEFORE_PPS,
.fgrain_support[0] = 1,
.fgrain_support[1] = 0,
.fgrain_support[2] = 0,
.has_hscaler_8tap[0] = 1,
.has_hscaler_8tap[1] = 1,
.has_hscaler_8tap[2] = 0,
.has_pre_hscaler_ntap[0] = 1,
.has_pre_hscaler_ntap[1] = 1,
.has_pre_hscaler_ntap[2] = 0,
.has_pre_vscaler_ntap[0] = 1,
.has_pre_vscaler_ntap[1] = 1,
.has_pre_vscaler_ntap[2] = 0,
.src_width_max[0] = 4096,
.src_width_max[1] = 2048,
.src_width_max[2] = 2048,
.src_height_max[0] = 2160,
.src_height_max[1] = 1080,
.src_height_max[2] = 1080,
.ofifo_size = 0x1000,
.afbc_conv_lbuf_len[0] = 0x100,
.afbc_conv_lbuf_len[1] = 0x100,
.mif_linear = 1,
.display_module = 0,
.max_vd_layers = 2,
.is_tv_panel = 0,
};
static struct video_device_hw_s legcy_dev_property = {
.vd2_independ_blend_ctrl = 0,
.aisr_support = 0,
@@ -14604,6 +14655,10 @@ static const struct of_device_id amlogic_amvideom_dt_match[] = {
.compatible = "amlogic, amvideom-s1a",
.data = &amvideo_s1a,
},
{
.compatible = "amlogic, amvideom-s7",
.data = &amvideo_s7,
},
#endif
{}
};
@@ -14734,6 +14789,15 @@ bool video_is_meson_s1a_cpu(void)
return false;
}
bool video_is_meson_s7_cpu(void)
{
if (amvideo_meson_dev.cpu_type ==
MESON_CPU_MAJOR_ID_S7_)
return true;
else
return false;
}
bool has_hscaler_8tap(u8 layer_id)
{
if (amvideo_meson_dev.has_hscaler_8tap[layer_id])
+8 -2
View File
@@ -13873,7 +13873,8 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo)
}
} else if (video_is_meson_sc2_cpu() ||
video_is_meson_s4_cpu() ||
video_is_meson_s1a_cpu()) {
video_is_meson_s1a_cpu() ||
video_is_meson_s7_cpu()) {
for (i = 0; i < cur_dev->max_vd_layers; i++) {
memcpy(&vd_layer[i].vd_afbc_reg,
&vd_afbc_reg_sc2_array[i],
@@ -13881,11 +13882,16 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo)
memcpy(&vd_layer[i].vd_mif_reg,
&vd_mif_reg_sc2_array[i],
sizeof(struct hw_vd_reg_s));
if (video_is_meson_s7_cpu())
memcpy(&vd_layer[i].vd_mif_linear_reg,
&vd_mif_linear_reg_t7_array[i],
sizeof(struct hw_vd_linear_reg_s));
memcpy(&vd_layer[i].fg_reg,
&fg_reg_sc2_array[i],
sizeof(struct hw_fg_reg_s));
if (video_is_meson_s4_cpu() ||
video_is_meson_s1a_cpu())
video_is_meson_s1a_cpu() ||
video_is_meson_s7_cpu())
memcpy(&vd_layer[i].pps_reg,
&pps_reg_array_t5d[i],
sizeof(struct hw_pps_reg_s));
+2
View File
@@ -630,6 +630,7 @@ enum cpu_type_e {
MESON_CPU_MAJOR_ID_T3X_,
MESON_CPU_MAJOR_ID_TXHD2_,
MESON_CPU_MAJOR_ID_S1A_,
MESON_CPU_MAJOR_ID_S7_,
MESON_CPU_MAJOR_ID_UNKNOWN_,
};
@@ -981,6 +982,7 @@ bool video_is_meson_t3x_cpu(void);
bool video_is_meson_t5m_cpu(void);
bool video_is_meson_txhd2_cpu(void);
bool video_is_meson_s1a_cpu(void);
bool video_is_meson_s7_cpu(void);
void alpha_win_set(struct video_layer_s *layer);
void fgrain_config(struct video_layer_s *layer,
struct vpp_frame_par_s *frame_par,