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t5m: fix gp0 unlock when resume. [1/2]
PD#SPWL-214643 Problem: gp0 pll can't lock when resume Solution: release lock limitation Verify: t5m ay301 Change-Id: I447bbaa03ab7204da5bc8e9f9858adff7d80bfb8 Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
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gerrit autosubmit
parent
c8c75d69c2
commit
7cf3f7c0cd
@@ -189,9 +189,10 @@ static struct clk_regmap t5m_fclk_div2p5 = {
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};
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static const struct pll_params_table t5m_gp0_pll_table[] = {
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PLL_PARAMS_OD(128, 1, 2), /* DCO = 3072M OD = 2 PLL = 768M */
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PLL_PARAMS_OD(96, 1, 1), /* DCO = 2304M OD = 1 PLL = 1152M */
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PLL_PARAMS_OD(128, 1, 1), /* DCO = 3072M OD = 1 PLL = 1536M */
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PLL_PARAMS_OD(256, 1, 2), /* DCO = 3072M OD = 2 PLL = 768M */
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PLL_PARAMS_OD(192, 1, 1), /* DCO = 2304M OD = 1 PLL = 1152M */
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PLL_PARAMS_OD(256, 1, 1), /* DCO = 3072M OD = 1 PLL = 1536M */
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PLL_PARAMS_OD(257, 1, 1), /* DCO = 3084M OD = 1 PLL = 1542M */
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{ /* sentinel */ }
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};
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@@ -201,7 +202,7 @@ static const struct pll_params_table t5m_gp0_pll_table[] = {
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static const struct reg_sequence t5m_gp0_init_regs[] = {
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{ .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x03a00000 },
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{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00040000 },
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{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x090da200 },
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{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x0e0da200 },
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};
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static struct clk_regmap t5m_gp0_pll = {
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@@ -245,7 +246,8 @@ static struct clk_regmap t5m_gp0_pll = {
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.od_max = 4,
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.init_regs = t5m_gp0_init_regs,
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.init_count = ARRAY_SIZE(t5m_gp0_init_regs),
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.flags = CLK_MESON_PLL_FIXED_N | CLK_MESON_PLL_NOINIT_ENABLED,
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.flags = CLK_MESON_PLL_FIXED_N | CLK_MESON_PLL_NOINIT_ENABLED |
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CLK_MESON_PLL_FIXED_EN0P5,
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},
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.hw.init = &(struct clk_init_data){
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.name = "gp0_pll",
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