G12B: Support HS200&HS400 for eMMC and SDR104 for SD. [1/1]

PD#SWPL-157501

Problem:
Not support HS200&HS400 for eMMC and SDR104 for SD in G12B.

Solution:
Add HS200&HS400 for eMMC and SDR104 for SD.

Verify:
g12b_w400_v1

Change-Id: I5deda6e2587ddd34f6d7bc7a86d95d8baa1c0efd
Signed-off-by: jinbiao <jinbiao.ou@amlogic.com>
This commit is contained in:
jinbiao
2024-02-05 06:43:59 +00:00
committed by gerrit autosubmit
parent 4261cbd15c
commit 8f5e831e6e
4 changed files with 71 additions and 74 deletions
+23 -25
View File
@@ -1422,17 +1422,15 @@
max-frequency = <200000000>;
non-removable;
disable-wp;
//mmc-ddr-1_8v;
//mmc-hs200-1_8v;
//mmc-hs400-1_8v;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
//mmc-pwrseq = <&emmc_pwrseq>;
//vmmc-supply = <&vcc_3v3>;
//vqmmc-supply = <&vddio_boot>;
};
&sd_emmc_b {
//vmmc-supply = <&vddao3v3_reg>;
//vqmmc-supply = <&vddio_c>;
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-1 = <&sdcard_clk_gate_pins>;
@@ -1449,26 +1447,26 @@
// &ao_to_sd_uart_pins>;
pinctrl-names = "sd_default",
"clk-gate",
"sd_1bit_pins";
// "sd_clk_cmd_uart_pins",
// "sd_1bit_uart_pins",
// "sd_to_ao_uart_pins",
// "ao_to_sd_uart_pins",
// "sd_to_ao_jtag_pins",
// "ao_to_sd_jtag_pins";
bus-width = <4>;
cap-sd-highspeed;
// sd-uhs-sdr12;
// sd-uhs-sdr25;
// sd-uhs-sdr50;
// sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
//vmmc-supply = <&vddao_3v3>;
//vqmmc-supply = <&emmc_1v8>;
"clk-gate",
"sd_1bit_pins";
// "sd_clk_cmd_uart_pins",
// "sd_1bit_uart_pins",
// "sd_to_ao_uart_pins",
// "ao_to_sd_uart_pins",
// "sd_to_ao_jtag_pins",
// "ao_to_sd_jtag_pins";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vddao3v3_reg>;
vqmmc-supply = <&vddio_c>;
};
&sd_emmc_a {
@@ -1430,7 +1430,7 @@
max-frequency = <200000000>;
non-removable;
disable-wp;
//mmc-ddr-1_8v;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
//mmc-pwrseq = <&emmc_pwrseq>;
@@ -1439,8 +1439,6 @@
};
&sd_emmc_b {
//vmmc-supply = <&vddao3v3_reg>;
//vqmmc-supply = <&vddio_c>;
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-1 = <&sdcard_clk_gate_pins>;
@@ -1457,26 +1455,26 @@
// &ao_to_sd_uart_pins>;
pinctrl-names = "sd_default",
"clk-gate",
"sd_1bit_pins";
// "sd_clk_cmd_uart_pins",
// "sd_1bit_uart_pins",
// "sd_to_ao_uart_pins",
// "ao_to_sd_uart_pins",
// "sd_to_ao_jtag_pins",
// "ao_to_sd_jtag_pins";
bus-width = <4>;
cap-sd-highspeed;
// sd-uhs-sdr12;
// sd-uhs-sdr25;
// sd-uhs-sdr50;
// sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
//vmmc-supply = <&vddao_3v3>;
//vqmmc-supply = <&emmc_1v8>;
"clk-gate",
"sd_1bit_pins";
// "sd_clk_cmd_uart_pins",
// "sd_1bit_uart_pins",
// "sd_to_ao_uart_pins",
// "ao_to_sd_uart_pins",
// "sd_to_ao_jtag_pins",
// "ao_to_sd_jtag_pins";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vddao3v3_reg>;
vqmmc-supply = <&vddio_c>;
};
&sd_emmc_a {
@@ -1428,17 +1428,15 @@
max-frequency = <200000000>;
non-removable;
disable-wp;
//mmc-ddr-1_8v;
//mmc-hs200-1_8v;
//mmc-hs400-1_8v;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
//mmc-pwrseq = <&emmc_pwrseq>;
//vmmc-supply = <&vcc_3v3>;
//vqmmc-supply = <&vddio_boot>;
};
&sd_emmc_b {
//vmmc-supply = <&vddao3v3_reg>;
//vqmmc-supply = <&vddio_c>;
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-1 = <&sdcard_clk_gate_pins>;
@@ -1455,26 +1453,26 @@
// &ao_to_sd_uart_pins>;
pinctrl-names = "sd_default",
"clk-gate",
"sd_1bit_pins";
// "sd_clk_cmd_uart_pins",
// "sd_1bit_uart_pins",
// "sd_to_ao_uart_pins",
// "ao_to_sd_uart_pins",
// "sd_to_ao_jtag_pins",
// "ao_to_sd_jtag_pins";
bus-width = <4>;
cap-sd-highspeed;
// sd-uhs-sdr12;
// sd-uhs-sdr25;
// sd-uhs-sdr50;
// sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
//vmmc-supply = <&vddao_3v3>;
//vqmmc-supply = <&emmc_1v8>;
"clk-gate",
"sd_1bit_pins";
// "sd_clk_cmd_uart_pins",
// "sd_1bit_uart_pins",
// "sd_to_ao_uart_pins",
// "ao_to_sd_uart_pins",
// "sd_to_ao_jtag_pins",
// "ao_to_sd_jtag_pins";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vddao3v3_reg>;
vqmmc-supply = <&vddio_c>;
};
&sd_emmc_a {
+4 -1
View File
@@ -1546,7 +1546,7 @@
reg = <0x0 0xffe07000 0x0 0x800>,
<0x0 0xffe07000 0x0 0x800>,
<0x0 0xffe07000 0x0 0x800>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
//interrupts = <0 191 1>;
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0_SEL>,
@@ -1556,6 +1556,9 @@
<&clkc CLKID_FCLK_DIV2P5>;
clock-names = "core","mux0","mux1","clkin0","clkin1","clkin2";
tx_delay = <16>;
//ignore_desc_busy;
hs4_core_phase = <0>;
hs4_tx_phase = <0>;
card_type = <1>;
mmc_debug_flag;
disable-wp;