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G12B: Support HS200&HS400 for eMMC and SDR104 for SD. [1/1]
PD#SWPL-157501 Problem: Not support HS200&HS400 for eMMC and SDR104 for SD in G12B. Solution: Add HS200&HS400 for eMMC and SDR104 for SD. Verify: g12b_w400_v1 Change-Id: I5deda6e2587ddd34f6d7bc7a86d95d8baa1c0efd Signed-off-by: jinbiao <jinbiao.ou@amlogic.com>
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gerrit autosubmit
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4261cbd15c
commit
8f5e831e6e
@@ -1422,17 +1422,15 @@
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max-frequency = <200000000>;
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non-removable;
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disable-wp;
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//mmc-ddr-1_8v;
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//mmc-hs200-1_8v;
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//mmc-hs400-1_8v;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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//mmc-pwrseq = <&emmc_pwrseq>;
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//vmmc-supply = <&vcc_3v3>;
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//vqmmc-supply = <&vddio_boot>;
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};
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&sd_emmc_b {
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//vmmc-supply = <&vddao3v3_reg>;
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//vqmmc-supply = <&vddio_c>;
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status = "okay";
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pinctrl-0 = <&sdcard_pins>;
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pinctrl-1 = <&sdcard_clk_gate_pins>;
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@@ -1449,26 +1447,26 @@
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// &ao_to_sd_uart_pins>;
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pinctrl-names = "sd_default",
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"clk-gate",
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"sd_1bit_pins";
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// "sd_clk_cmd_uart_pins",
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// "sd_1bit_uart_pins",
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// "sd_to_ao_uart_pins",
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// "ao_to_sd_uart_pins",
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// "sd_to_ao_jtag_pins",
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// "ao_to_sd_jtag_pins";
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bus-width = <4>;
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cap-sd-highspeed;
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// sd-uhs-sdr12;
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// sd-uhs-sdr25;
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// sd-uhs-sdr50;
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// sd-uhs-sdr104;
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max-frequency = <200000000>;
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disable-wp;
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dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
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//vmmc-supply = <&vddao_3v3>;
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//vqmmc-supply = <&emmc_1v8>;
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"clk-gate",
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"sd_1bit_pins";
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// "sd_clk_cmd_uart_pins",
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// "sd_1bit_uart_pins",
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// "sd_to_ao_uart_pins",
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// "ao_to_sd_uart_pins",
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// "sd_to_ao_jtag_pins",
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// "ao_to_sd_jtag_pins";
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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max-frequency = <200000000>;
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disable-wp;
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dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <&vddao3v3_reg>;
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vqmmc-supply = <&vddio_c>;
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};
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&sd_emmc_a {
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@@ -1430,7 +1430,7 @@
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max-frequency = <200000000>;
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non-removable;
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disable-wp;
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//mmc-ddr-1_8v;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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//mmc-pwrseq = <&emmc_pwrseq>;
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@@ -1439,8 +1439,6 @@
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};
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&sd_emmc_b {
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//vmmc-supply = <&vddao3v3_reg>;
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//vqmmc-supply = <&vddio_c>;
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status = "okay";
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pinctrl-0 = <&sdcard_pins>;
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pinctrl-1 = <&sdcard_clk_gate_pins>;
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@@ -1457,26 +1455,26 @@
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// &ao_to_sd_uart_pins>;
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pinctrl-names = "sd_default",
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"clk-gate",
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"sd_1bit_pins";
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// "sd_clk_cmd_uart_pins",
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// "sd_1bit_uart_pins",
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// "sd_to_ao_uart_pins",
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// "ao_to_sd_uart_pins",
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// "sd_to_ao_jtag_pins",
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// "ao_to_sd_jtag_pins";
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bus-width = <4>;
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cap-sd-highspeed;
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// sd-uhs-sdr12;
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// sd-uhs-sdr25;
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// sd-uhs-sdr50;
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// sd-uhs-sdr104;
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max-frequency = <200000000>;
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disable-wp;
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dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
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//vmmc-supply = <&vddao_3v3>;
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//vqmmc-supply = <&emmc_1v8>;
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"clk-gate",
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"sd_1bit_pins";
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// "sd_clk_cmd_uart_pins",
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// "sd_1bit_uart_pins",
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// "sd_to_ao_uart_pins",
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// "ao_to_sd_uart_pins",
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// "sd_to_ao_jtag_pins",
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// "ao_to_sd_jtag_pins";
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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max-frequency = <200000000>;
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disable-wp;
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dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <&vddao3v3_reg>;
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vqmmc-supply = <&vddio_c>;
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};
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&sd_emmc_a {
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@@ -1428,17 +1428,15 @@
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max-frequency = <200000000>;
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non-removable;
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disable-wp;
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//mmc-ddr-1_8v;
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//mmc-hs200-1_8v;
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//mmc-hs400-1_8v;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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//mmc-pwrseq = <&emmc_pwrseq>;
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//vmmc-supply = <&vcc_3v3>;
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//vqmmc-supply = <&vddio_boot>;
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};
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&sd_emmc_b {
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//vmmc-supply = <&vddao3v3_reg>;
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//vqmmc-supply = <&vddio_c>;
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status = "okay";
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pinctrl-0 = <&sdcard_pins>;
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pinctrl-1 = <&sdcard_clk_gate_pins>;
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@@ -1455,26 +1453,26 @@
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// &ao_to_sd_uart_pins>;
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pinctrl-names = "sd_default",
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"clk-gate",
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"sd_1bit_pins";
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// "sd_clk_cmd_uart_pins",
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// "sd_1bit_uart_pins",
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// "sd_to_ao_uart_pins",
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// "ao_to_sd_uart_pins",
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// "sd_to_ao_jtag_pins",
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// "ao_to_sd_jtag_pins";
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bus-width = <4>;
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cap-sd-highspeed;
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// sd-uhs-sdr12;
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// sd-uhs-sdr25;
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// sd-uhs-sdr50;
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// sd-uhs-sdr104;
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max-frequency = <200000000>;
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disable-wp;
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dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
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//vmmc-supply = <&vddao_3v3>;
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//vqmmc-supply = <&emmc_1v8>;
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"clk-gate",
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"sd_1bit_pins";
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// "sd_clk_cmd_uart_pins",
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// "sd_1bit_uart_pins",
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// "sd_to_ao_uart_pins",
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// "ao_to_sd_uart_pins",
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// "sd_to_ao_jtag_pins",
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// "ao_to_sd_jtag_pins";
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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max-frequency = <200000000>;
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disable-wp;
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dat1-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <&vddao3v3_reg>;
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vqmmc-supply = <&vddio_c>;
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};
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&sd_emmc_a {
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@@ -1546,7 +1546,7 @@
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reg = <0x0 0xffe07000 0x0 0x800>,
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<0x0 0xffe07000 0x0 0x800>,
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<0x0 0xffe07000 0x0 0x800>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
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//interrupts = <0 191 1>;
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clocks = <&clkc CLKID_SD_EMMC_C>,
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<&clkc CLKID_SD_EMMC_C_CLK0_SEL>,
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@@ -1556,6 +1556,9 @@
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<&clkc CLKID_FCLK_DIV2P5>;
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clock-names = "core","mux0","mux1","clkin0","clkin1","clkin2";
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tx_delay = <16>;
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//ignore_desc_busy;
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hs4_core_phase = <0>;
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hs4_tx_phase = <0>;
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card_type = <1>;
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mmc_debug_flag;
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disable-wp;
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