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vpu_security: add fg secure for s7 [1/1]

Browse Source 
PD#SWPL-155917

Problem:
add fg secure for s7

Solution:
complete it

Verify:
s7

Change-Id: I8714a4070d997a559ecccca845fa7810bae50e83
Signed-off-by: yuhua.lin <yuhua.lin@amlogic.com>
This commit is contained in:
yuhua.lin
2024-01-26 17:20:47 +08:00
committed by gerrit autosubmit
parent 09ee75c0b7
commit 93bc4ffb25
6 changed files with 58 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-s7.dtsi
+1 -1
View File
@@ -1552,7 +1552,7 @@
};
vpu_security {
compatible = "amlogic, meson-s4, vpu_security";
compatible = "amlogic, meson-s7, vpu_security";
dev_name = "amlogic-vpu-security";
status = "okay";
interrupts = <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
drivers/media/common/vpu_security/vpu_security.c
+37 -2
View File
@@ -110,6 +110,25 @@ static struct vpu_sec_reg_s reg_v4[] = {
{S5_VIU_VD4_MISC, 1, 4, 1}, /* 12. 02.1 vd1 slice 3 */
};
static struct vpu_sec_reg_s reg_v5[] = {
{VIU_DATA_SEC, 1, 0, 1}, /* 00. OSD1 */
{VIU_DATA_SEC, 1, 1, 1}, /* 01. OSD2 */
{VIU_DATA_SEC, 1, 2, 1}, /* 02. VD1 */
{VIU_DATA_SEC, 1, 3, 1}, /* 03. VD2 */
{VIU_DATA_SEC, 1, 4, 1}, /* 04. OSD3 */
{VIU_DATA_SEC, 1, 5, 1}, /* 05. VD AFBC, not used */
{VIU_DATA_SEC, 1, 6, 1}, /* 06. DV */
{VIU_DATA_SEC, 1, 7, 1}, /* 07. OSD AFBC */
{VIU_DATA_SEC, 1, 8, 1}, /* 08. VPP_TOP */
{0, 1, 0, 1}, /* 09. OSD4, not used */
{0, 1, 0, 1}, /* 10. VD3, not used */
{0, 1, 0, 1}, /* 11. VPP_TOP1, not used */
{0, 1, 0, 1}, /* 12. VPP_TOP2, not used */
{VPU_LUT_DMA_SEC_IN, 1, 0, 1}, /* 13. VD1 FG */
{VPU_LUT_DMA_SEC_IN, 1, 1, 1}, /* 14. VD2 FG */
{VPU_LUT_DMA_SEC_IN, 1, 2, 1} /* 15. DI FG */
};
static struct sec_dev_data_s vpu_security_sc2 = {
.version = VPU_SEC_V1,
};
@@ -131,6 +150,10 @@ static struct sec_dev_data_s vpu_security_t3 = {
static struct sec_dev_data_s vpu_security_s5 = {
.version = VPU_SEC_V4,
};
static struct sec_dev_data_s vpu_security_s7 = {
.version = VPU_SEC_V5,
};
#endif
static const struct of_device_id vpu_security_dt_match[] = {
@@ -157,6 +180,10 @@ static const struct of_device_id vpu_security_dt_match[] = {
.compatible = "amlogic, meson-s5, vpu_security",
.data = &vpu_security_s5,
},
{
.compatible = "amlogic, meson-s7, vpu_security",
.data = &vpu_security_s7,
},
#endif
{}
};
@@ -243,6 +270,9 @@ static void secure_reg_update(struct vpu_secure_ins *ins,
} else if (version == VPU_SEC_V4) {
reg_size = ARRAY_SIZE(reg_v4);
reg_item = &reg_v4[0];
} else if (version == VPU_SEC_V5) {
reg_size = ARRAY_SIZE(reg_v5);
reg_item = &reg_v5[0];
}
/* work through the array and write bit(s) */
@@ -314,7 +344,9 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
}
break;
case VIDEO_MODULE:
if ((secure_src & DV_INPUT_SECURE) ||
if ((secure_src & VD2_FGRAIN_SECURE) ||
(secure_src & VD1_FGRAIN_SECURE) ||
(secure_src & DV_INPUT_SECURE) ||
(secure_src & AFBCD_INPUT_SECURE) ||
(secure_src & VD3_INPUT_SECURE) ||
(secure_src & VD2_INPUT_SECURE) ||
@@ -354,7 +386,7 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
break;
}
if (version < VPU_SEC_V4) {
if (version < VPU_SEC_V4 || version == VPU_SEC_V5) {
vpp_top_en = osd_secure_en[vpp_index] ||
video_secure_en[vpp_index];
if (vpp_index == 0) {
@@ -539,6 +571,9 @@ static ssize_t debug_value_show(struct class *cla,
len += sprintf(buf + len, "bit10. VD3\n");
len += sprintf(buf + len, "bit11. VPP_TOP1\n");
len += sprintf(buf + len, "bit12. VPP_TOP2\n");
len += sprintf(buf + len, "bit13. VD1_FGRAIN\n");
len += sprintf(buf + len, "bit14. VD2_FGRAIN\n");
len += sprintf(buf + len, "bit15. DI_FGRAIN\n");
return len;
}
drivers/media/common/vpu_security/vpu_security.h
+1
View File
@@ -32,6 +32,7 @@ enum vpu_security_version_e {
VPU_SEC_V2,
VPU_SEC_V3,
VPU_SEC_V4,
VPU_SEC_V5,
VPU_SEC_MAX
};
drivers/media/common/vpu_security/vpu_security_reg.h
+1
View File
@@ -15,5 +15,6 @@
#define S5_VIU_OSD2_MISC 0x1a16
#define S5_VIU_OSD3_MISC 0x1a17
#define S5_VIU_OSD4_MISC 0x1a18
#define VPU_LUT_DMA_SEC_IN 0x2709
#endif
drivers/media/video_sink/video_hw.c
+13
View File
@@ -13043,6 +13043,7 @@ void video_secure_set(u8 vpp_index)
int i;
u32 secure_src = 0;
u32 secure_enable = 0;
u32 fg_secure_enable = 0;
struct video_layer_s *layer = NULL;
for (i = 0; i < MAX_VD_LAYERS; i++) {
@@ -13056,6 +13057,11 @@ void video_secure_set(u8 vpp_index)
secure_enable = 1;
else
secure_enable = 0;
if (layer->dispbuf && layer->dispbuf->fgs_valid)
fg_secure_enable = 1;
else
fg_secure_enable = 0;
if (layer->dispbuf)
cur_vf_flag[layer->layer_id] = layer->dispbuf->flag;
if (layer->dispbuf &&
@@ -13067,6 +13073,13 @@ void video_secure_set(u8 vpp_index)
else if (layer->layer_id == 2)
secure_src |= VD3_INPUT_SECURE;
}
if (layer->dispbuf &&
fg_secure_enable) {
if (layer->layer_id == 0)
secure_src |= VD1_FGRAIN_SECURE;
else if (layer->layer_id == 1)
secure_src |= VD2_FGRAIN_SECURE;
}
}
secure_config(VIDEO_MODULE, secure_src, vpp_index);
#endif
include/linux/amlogic/media/vpu_secure/vpu_secure.h
+5
View File
@@ -32,6 +32,11 @@ enum module_port_e {
MAX_SECURE_OUT
};
/* v5 extern secure bits */
#define DI_FGRAIN_SECURE BIT(15)
#define VD2_FGRAIN_SECURE BIT(14)
#define VD1_FGRAIN_SECURE BIT(13)
/* v4 extern secure bits */
#define VD1_SLICE3_SECURE BIT(12)
#define VD1_SLICE2_SECURE BIT(11)