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amdv: case5356 fail [1/1]

Browse Source 
PD#SWPL-144183

Problem:
case5356 fail

Solution:
1.reset controlpath at hdmi first frame
2.improve hist read and write logic in cert mode
3.disable top2 interrupt when top1 enable

Verify:
t3x

Change-Id: I2ddd80eedf2148272e814aba75de4124f0f5639d
Signed-off-by: yao liu <yao.liu@amlogic.com>
This commit is contained in:
yao liu
2023-12-21 16:39:05 +08:00
committed by Luan Yuan
parent 6db09b3630
commit 94316d64bb
4 changed files with 45 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/enhancement/amdolby_vision/amdv.c
+13 -5
View File
@@ -11333,21 +11333,29 @@ void calculate_crc(void)
crc = READ_VPP_DV_REG(T3X_VENC_CRC);
snprintf(cur_crc, sizeof(cur_crc), "0x%08x", crc);
if (debug_dolby & 0x2000)
pr_info("CRC input 0x%x,output 0x%x\n",
pr_info("CRC input 0x%x,output 0x%x,write %x\n",
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_IN_FRM),
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_OUT_FRM));
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_OUT_FRM),
crc);
//}
crc_count++;
crc_read_delay = 0;
}
} else {
if ((debug_dolby & 0x2000) && is_aml_hw5())
pr_info("CRC input 0x%x, output 0x%x, venc crc %x\n",
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_IN_FRM),
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_OUT_FRM),
venc_crc_enable ?
READ_VPP_DV_REG(T3X_VENC_CRC) : 0);
}
}
} else if ((dolby_vision_flags & FLAG_CERTIFICATION) && is_aml_hw5()) {
if (debug_dolby & 0x2000)
pr_info("CRC input 0x%x, output 0x%x\n",
pr_info("CRC input 0x%x, output 0x%x, venc crc %x\n",
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_IN_FRM),
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_OUT_FRM));
READ_VPP_DV_REG(DOLBY5_CORE2_CRC_OUT_FRM),
venc_crc_enable ? READ_VPP_DV_REG(T3X_VENC_CRC) : 0);
}
}
drivers/media/enhancement/amdolby_vision/amdv.h
+2 -1
View File
@@ -9,7 +9,7 @@
/*#define V2_4_3*/
/* driver version */
#define DRIVER_VER "202301020"
#define DRIVER_VER "202301221"
#include <linux/types.h>
#include "amdv_pq_config.h"
@@ -108,6 +108,7 @@
#define DEBUG_AUTOMATICALLY_PYRAMID 0x800
#define DEBUG_FORCE_BYPASS_TOP2 0x1000
#define HDMI_ONLY_UPDATE_HIST_FOR_NEW_FRAME 0x2000 /*case5351 5356*/
#define FORCE_ONE_SLICE 0x4000 /*case5011b 5055a 5055b*/
#define MAX_CFG_SIZE (1024 * 10)
#define MAX_BIN_SIZE (1024 * 150)
drivers/media/enhancement/amdolby_vision/amdv_hw5.c
+23 -5
View File
@@ -1850,7 +1850,7 @@ int tv_top2_set(u64 *reg_data,
if (!enable_top1 || (test_dv & DEBUG_ENABLE_TOP2_INT))
VSYNC_WR_DV_REG_BITS(VPU_DOLBY_WRAP_IRQ, 1, 1, 1); //top2 dolby int, pulse
else
VSYNC_WR_DV_REG_BITS(VPU_DOLBY_WRAP_IRQ, 1, 0, 1); //top2 dolby int, disable
VSYNC_WR_DV_REG_BITS(VPU_DOLBY_WRAP_IRQ, 0, 1, 1); //top2 dolby int, disable
py_stride[0] = top1_stride_rdmif(1024, 10);
py_stride[1] = top1_stride_rdmif(512, 10);
@@ -2112,6 +2112,8 @@ void set_l1l4_hist(void)
u32 metadata0;
u32 metadata1;
u8 hist_test[256];
static bool hist_changed;
static u32 changed_count;
if (!tv_hw5_setting || !enable_top1)
return;
@@ -2125,12 +2127,28 @@ void set_l1l4_hist(void)
if ((dolby_vision_flags & FLAG_CERTIFICATION) &&
(test_dv & HDMI_ONLY_UPDATE_HIST_FOR_NEW_FRAME)) {
/*hdmi case, check hist and only update index for new frame*/
memcpy(&hist_test[0], dv5_md_hist.hist_vaddr[0], 256);
if (memcmp(&hist_test[0], &dv5_md_hist.hist[0], 256)) {
l1l4_wr_index = (l1l4_wr_index + 1) % HIST_BUF_COUNT;
memcpy(&hist_test[0], dv5_md_hist.hist_vaddr[0], 256);/*cur hist*/
if (memcmp(&hist_test[0], &dv5_md_hist.hist[0], 256) &&
top1_info.core_on_cnt > 4) {/*compare with last hist*/
hist_changed = true;
changed_count = 0;
memcpy(&dv5_md_hist.hist[0],
dv5_md_hist.hist_vaddr[0], 256);
if (debug_dolby & 1)
pr_info("hist change!\n");
return;
} else if (hist_changed) {
/*update after 4 times because checking vf_crc repeat 3*/
changed_count++;
if (debug_dolby & 1)
pr_info("changed_count %d\n", changed_count);
if (changed_count > 4) {
l1l4_wr_index = (l1l4_wr_index + 1) %
HIST_BUF_COUNT;
hist_changed = false;
} else {
return;
}
}
} else {
l1l4_wr_index = (l1l4_wr_index + 1) % HIST_BUF_COUNT;
drivers/media/enhancement/amdolby_vision/amdv_hw5_process.c
+7
View File
@@ -2323,6 +2323,8 @@ int amdv_parse_metadata_hw5(struct vframe_s *vf,
content_fps = variable_fps[hdmi_frame_count];
if (debug_dolby & 1)
pr_dv_dbg("variable_fps %d\n", content_fps);
} else if ((dolby_vision_flags & FLAG_CERTIFICATION) && (test_dv & FORCE_ONE_SLICE)) {
content_fps = 60000;
}
if (debug_dolby & 0x200)
pr_dv_dbg("[count %d %d]dark_detail from cfg:%d,from api:%d\n",
@@ -2398,6 +2400,11 @@ int amdv_parse_metadata_hw5(struct vframe_s *vf,
if (run_control_path) {
/*step2: top2 frame N-1*/
tv_hw5_setting->analyzer = 0;
if ((dolby_vision_flags & FLAG_CERTIFICATION) &&
vf && vf->source_type == VFRAME_SOURCE_TYPE_HDMI &&
hdmi_frame_count == 0)
p_funcs_tv->tv_hw5_control_path(invalid_hw5_setting);
flag = p_funcs_tv->tv_hw5_control_path(tv_hw5_setting);
if (debug_dolby & 0x400) {