shinys000114/kernel_common_drivers
1
0
Fork 0
mirror of https://github.com/hardkernel/kernel_common_drivers.git synced 2026-06-25 12:03:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

reset: c3: support reset driver [1/1]

Browse Source 
PD#SWPL-74266

Problem:
need to support c3 reset driver

Solution:
add reset dt-bindings and dts node for c3

Verify:
c3_pxp

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
Change-Id: I39f9dc7313002bf003cbc638d8835ef7ab5cbc4b
This commit is contained in:
Zelong Dong
2022-03-18 21:11:30 +08:00
committed by Hanjie Lin
parent e396a77753
commit 97371ec8cd
2 changed files with 123 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/boot/dts/amlogic/meson-c3.dtsi
+4 -4
View File
@@ -11,7 +11,7 @@
#include <dt-bindings/clock/a1-audio-clk.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/reset/amlogic,meson-c2-reset.h>
#include <dt-bindings/reset/amlogic,meson-c3-reset.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/meson_ir.h>
#include "meson-ir-map.dtsi"
@@ -374,9 +374,9 @@
#size-cells = <1>;
ranges = <0x0 0xfe000000 0x480000>;
reset: reset-controller@0x0 {
compatible = "amlogic,meson-c2-reset";
reg = <0x0 0x8c>;
reset: reset-controller@0x2000 {
compatible = "amlogic,meson-sc2-reset";
reg = <0x2000 0x98>;
#reset-cells = <1>;
};
include/dt-bindings/reset/amlogic,meson-c3-reset.h
+119
View File
@@ -0,0 +1,119 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_AMLOGIC_MESON_C3_RESET_H
#define _DT_BINDINGS_AMLOGIC_MESON_C3_RESET_H
/* RESET0 */
/* 0-3 */
#define RESET_USBCTRL 4
/* 5-7 */
#define RESET_USBPHY20 8
/* 9 */
#define RESET_USB2DRD 10
#define RESET_MIPI_DSI_HOST 11
#define RESET_MIPI_DSI_PHY 12
/* 13-20 */
#define RESET_GE2D 21
#define RESET_DWAP 22
/* 23-31 */
/* RESET1 */
#define RESET_AUDIO 32
/* 33-34 */
#define RESET_DDRAPB 35
#define RESET_DDR 36
#define RESET_DOS_CAPB3 37
#define RESET_DOS 38
/* 39-46 */
#define RESET_NNA 47
#define RESET_ETHERNET 48
#define RESET_ISP 49
#define RESET_VC9000E_APB 50
#define RESET_VC9000E_A 51
/* 52 */
#define RESET_VC9000E_CORE 53
/* 54-63 */
/* RESET2 */
#define RESET_ABUS_ARB 64
#define RESET_IRCTRL 65
/* 66 */
#define RESET_TEMP_PII 67
/* 68-72 */
#define RESET_SPICC_0 73
#define RESET_SPICC_1 74
#define RESET_RSA 75
/* 76-79 */
#define RESET_MSR_CLK 80
#define RESET_SPIFC 81
#define RESET_SAR_ADC 82
/* 83-87 */
#define RESET_ACODEC 88
/* 89-90 */
#define RESET_WATCHDOG 91
/* 92-95 */
/* RESET3 */
#define RESET_ISP_NIC_GPV 96
#define RESET_ISP_NIC_MAIN 97
#define RESET_ISP_NIC_VCLK 98
#define RESET_ISP_NIC_VOUT 99
#define RESET_ISP_NIC_ALL 100
#define RESET_VOUT 101
#define RESET_VOUT_VENC 102
/* 103 */
#define RESET_CVE_NIC_GPV 104
#define RESET_CVE_NIC_MAIN 105
#define RESET_CVE_NIC_GE2D 106
#define RESET_CVE_NIC_DW 106
#define RESET_CVE_NIC_CVE 108
#define RESET_CVE_NIC_ALL 109
#define RESET_CVE 110
/* 112-127 */
/* RESET4 */
#define RESET_RTC 128
#define RESET_PWM_AB 129
#define RESET_PWM_CD 130
#define RESET_PWM_EF 131
#define RESET_PWM_GH 132
#define RESET_PWM_IJ 133
#define RESET_PWM_KL 134
#define RESET_PWM_MN 135
/* 136-137 */
#define RESET_UART_A 138
#define RESET_UART_B 139
#define RESET_UART_C 140
#define RESET_UART_D 141
#define RESET_UART_E 142
#define RESET_UART_F 143
#define RESET_I2C_S_A 144
#define RESET_I2C_M_A 145
#define RESET_I2C_M_B 146
#define RESET_I2C_M_C 147
#define RESET_I2C_M_D 148
/* 149-151 */
#define RESET_SDEMMC_A 152
#define RESET_SDEMMC_B 153
#define RESET_SDEMMC_C 154
/* RESET5 */
/* 160-172 */
#define RESET_BRG_NIC_NNA 173
#define RESET_BRG_MUX_NIC_MAIN 174
#define RESET_BRG_AO_NIC_ALL 175
/* 176-183 */
#define RESET_BRG_NIC_VAPB 184
#define RESET_BRG_NIC_SDIO_B 185
#define RESET_BRG_NIC_SDIO_A 186
#define RESET_BRG_NIC_EMMC 187
#define RESET_BRG_NIC_DSU 188
#define RESET_BRG_NIC_SYSCLK 189
#define RESET_BRG_NIC_MAIN 190
#define RESET_BRG_NIC_ALL 191
#endif