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vpp: vpp0 rdma write delay 1 vsync [1/1]

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PD#SWPL-145037

Problem:
vpp1 render called vpp0 rdma write caused
vpp0 rdma write delay 1 vsync

Solution:
correct vpp0/vpp1 rdma write index

Verify:
T3X

Change-Id: I5d0563fea13c3402f0512d4bbd6ae44b4041e4b9
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
This commit is contained in:
Pengcheng Chen
2023-11-24 19:21:41 +08:00
committed by Luan Yuan
parent 33111924fe
commit 9ec9d11ebd
4 changed files with 52 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/video_sink/video.c
+4 -4
View File
@@ -14309,11 +14309,11 @@ static struct amvideo_device_data_s amvideo_t3x = {
.has_pre_vscaler_ntap[0] = 1,
.has_pre_vscaler_ntap[1] = 1,
.has_pre_vscaler_ntap[2] = 0,
.src_width_max[0] = 8192,
.src_width_max[1] = 8192,
.src_width_max[0] = 4096,
.src_width_max[1] = 4096,
.src_width_max[2] = 4096,
.src_height_max[0] = 4320,
.src_height_max[1] = 4320,
.src_height_max[0] = 2160,
.src_height_max[1] = 2160,
.src_height_max[2] = 2160,
.ofifo_size = 0x800,
.afbc_conv_lbuf_len[0] = 0x100,
drivers/media/video_sink/video_func.c
+3 -1
View File
@@ -1418,7 +1418,7 @@ void primary_swap_frame(struct video_layer_s *layer,
int crop[4];
struct vframe_s *vf;
#ifdef CONFIG_AMLOGIC_MEDIA_DEINTERLACE
u32 vpp_index = VPP0;
u32 vpp_index = layer->vpp_index;
#endif
ATRACE_COUNTER(__func__, line);
@@ -4078,6 +4078,8 @@ static void misc_late_proc(void)
first_irq = false;
goto RUN_FIRST_RDMA;
}
//if (new_frame_mask && is_vsync_rdma_enable())
// update_over_field_states(OVER_FIELD_NEW_VF, false);
for (i = 0; i < cur_dev->max_vd_layers; i++)
if (vd_layer[i].vd_func.vd_misc_late_proc)
drivers/media/video_sink/video_hw.c
+8 -7
View File
@@ -5468,6 +5468,7 @@ void switch_3d_view_per_vsync(struct video_layer_s *layer)
if (!layer || !layer->cur_frame_par || !layer->dispbuf)
return;
vpp_index = layer->vpp_index;
if (cur_dev->display_module == S5_DISPLAY_MODULE) {
switch_3d_view_per_vsync_s5(layer);
return;
@@ -6523,7 +6524,7 @@ static void check_video_mute_state(void)
static inline void mute_vpp(void)
{
u32 black_val;
u8 vpp_index = VPP0;
u8 vpp_index = vd_layer[0].vpp_index;
struct clip_setting_s setting;
black_val = (0x0 << 20) | (0x200 << 10) | 0x200; /* YUV */
@@ -6549,7 +6550,7 @@ static inline void mute_vpp(void)
static inline void unmute_vpp(void)
{
u8 vpp_index = VPP0;
u8 vpp_index = vd_layer[0].vpp_index;
struct clip_setting_s setting;
setting.clip_done = false;
@@ -9352,10 +9353,10 @@ static void set_mosaic_vframe_info(struct video_layer_s *layer,
layer->pi_enable = 0;
layer->vd1s1_vd2_prebld_en = 0;
g_mosaic_mode = 1;
enable_mosaic_mode(VPP0, 1);
enable_mosaic_mode(layer->vpp_index, 1);
} else {
g_mosaic_mode = 0;
enable_mosaic_mode(VPP0, 0);
enable_mosaic_mode(layer->vpp_index, 0);
}
layer->mosaic_mode = g_mosaic_mode;
if (layer->mosaic_mode) {
@@ -9608,7 +9609,7 @@ int set_layer_display_canvas(struct video_layer_s *layer,
if (layer->layer_id == 0 && layer->slice_num > 1) {
if (layer->mosaic_mode)
vd_switch_frm_idx(VPP0, frame_id);
vd_switch_frm_idx(layer->vpp_index, frame_id);
for (slice = 0; slice < layer->slice_num; slice++) {
if (layer->vd1s1_vd2_prebld_en &&
layer->slice_num == 2 &&
@@ -9629,7 +9630,7 @@ int set_layer_display_canvas(struct video_layer_s *layer,
}
if (layer->mosaic_mode) {
frame_id = 1;
vd_switch_frm_idx(VPP0, frame_id);
vd_switch_frm_idx(layer->vpp_index, frame_id);
for (slice = 0; slice < layer->slice_num; slice++) {
/* switch frame, set pic2/3 */
set_layer_mosaic_display_canvas_s5(layer, vf,
@@ -9637,7 +9638,7 @@ int set_layer_display_canvas(struct video_layer_s *layer,
}
layer->mosaic_frame = true;
frame_id = 0;
vd_switch_frm_idx(VPP0, frame_id);
vd_switch_frm_idx(layer->vpp_index, frame_id);
}
return 0;
}
drivers/media/video_sink/video_hw_s5.c
+37 -29
View File
@@ -1871,13 +1871,13 @@ static void vd_proc_sr0_set(u32 vpp_index,
if ((tmp_data & 0x1) != 0)
rdma_wr_bits(vd_sr_slice_reg->vd_proc_sr0_ctrl,
0, 0, 1);
vpu_module_clk_disable_s5(VPP0, SR0, 0);
vpu_module_clk_disable_s5(vpp_index, SR0, 0);
} else {
if (((tmp_data >> 1) & 0x1) != 1)
rdma_wr_bits(vd_sr_slice_reg->vd_proc_sr0_ctrl,
1, 1, 1);
if ((tmp_data & 0x1) != 1)
vpu_module_clk_enable_s5(VPP0, SR0, 0);
vpu_module_clk_enable_s5(vpp_index, SR0, 0);
rdma_wr_bits(vd_sr_slice_reg->vd_proc_sr0_ctrl, 1, 0, 1);
}
@@ -1960,7 +1960,7 @@ static void vd_proc_sr1_set(u32 vpp_index,
pr_info("%s:disable sr1 core tmp_data: %x\n",
__func__,
tmp_data);
vpu_module_clk_disable_s5(VPP0, SR1, 0);
vpu_module_clk_disable_s5(vpp_index, SR1, 0);
} else {
if (debug_flag_s5 & DEBUG_SR)
pr_info("%s:enable sr1 core tmp_data: %x\n",
@@ -1970,7 +1970,7 @@ static void vd_proc_sr1_set(u32 vpp_index,
rdma_wr_bits(vd_sr_slice_reg->vd_proc_sr1_ctrl,
1, 1, 1);
if ((tmp_data & 0x1) != 1)
vpu_module_clk_enable_s5(VPP0, SR1, 0);
vpu_module_clk_enable_s5(vpp_index, SR1, 0);
rdma_wr_bits(vd_sr_slice_reg->vd_proc_sr1_ctrl, 1, 0, 1);
}
@@ -2502,11 +2502,12 @@ static struct mosaic_frame_s *get_mosaic_frame(u32 slice)
return mosaic_frame;
}
static void vd1_proc_set(u32 vpp_index, struct vd_proc_s *vd_proc)
static void vd1_proc_set(struct video_layer_s *layer,
struct vd_proc_s *vd_proc)
{
int i;
struct vd_proc_unit_s *vd_proc_unit;
u32 vpp_index = layer->vpp_index;
vd_proc_bypass_preblend(vpp_index, vd_proc);
for (i = 0; i < vd_proc->vd_proc_vd1_info.slice_num; i++) {
@@ -2521,7 +2522,7 @@ static void vd1_proc_set(u32 vpp_index, struct vd_proc_s *vd_proc)
vd_proc_unit_set(vpp_index, vd_proc_unit);
/* pps */
if (!vd_layer[0].mosaic_mode) {
vd1_scaler_setting_s5(&vd_layer[0], &vd_layer[0].sc_setting, i);
vd1_scaler_setting_s5(layer, &layer->sc_setting, i);
} else {
struct mosaic_frame_s *mosaic_frame = NULL;
struct video_layer_s *virtual_layer = NULL;
@@ -2576,14 +2577,14 @@ static void vd_3mux3_set(u8 vpp_index)
}
}
static void vd2_proc_set(u32 vpp_index, struct vd2_proc_s *vd2_proc)
static void vd2_proc_set(struct video_layer_s *layer,
struct vd2_proc_s *vd2_proc)
{
u32 vpp_index = layer->vpp_index;
struct vd2_proc_misc_reg_s *vd2_proc_misc_reg = NULL;
rdma_wr_op rdma_wr = cur_dev->rdma_func[vpp_index].rdma_wr;
rdma_wr_bits_op rdma_wr_bits = cur_dev->rdma_func[vpp_index].rdma_wr_bits;
struct video_layer_s *layer = NULL;
layer = get_vd_layer(1);
vd2_proc_misc_reg = &vd_proc_reg.vd2_proc_misc_reg;
rdma_wr(vd2_proc_misc_reg->vd2_proc_in_size,
vd2_proc->din_hsize << 16 |
@@ -2594,9 +2595,9 @@ static void vd2_proc_set(u32 vpp_index, struct vd2_proc_s *vd2_proc)
vd2_proc_bypass_hdr(vpp_index, vd2_proc->bypass_hdr);
/* pps */
if (vd2_proc->bypass_pps) {
vd_layer[1].sc_setting.sc_top_enable = false;
vd_layer[1].sc_setting.sc_h_enable = false;
vd_layer[1].sc_setting.sc_v_enable = false;
layer->sc_setting.sc_top_enable = false;
layer->sc_setting.sc_h_enable = false;
layer->sc_setting.sc_v_enable = false;
}
vdx_scaler_setting_s5(layer, &layer->sc_setting);
if (vd2_proc->vd2_dout_dpsel == VD2_DOUT_PI) {
@@ -2617,12 +2618,14 @@ static void vd2_proc_set(u32 vpp_index, struct vd2_proc_s *vd2_proc)
vd_3mux3_set(vpp_index);
}
static void vd_proc_set(u32 vpp_index, struct vd_proc_s *vd_proc)
static void vd_proc_set(struct video_layer_s *layer,
struct vd_proc_s *vd_proc)
{
u32 vd1_work_mode = 0;
u32 vd1_slices_dout_dpsel = 0;
u32 mosaic_mode, hsize = 0;
u32 vd1_dout_hsize = 0, vd1_dout_vsize = 0;
u32 vpp_index = layer->vpp_index;
rdma_wr_op rdma_wr = cur_dev->rdma_func[vpp_index].rdma_wr;
rdma_wr_bits_op rdma_wr_bits = cur_dev->rdma_func[vpp_index].rdma_wr_bits;
struct vd_proc_mosaic_s *vd_proc_mosaic = NULL;
@@ -2642,13 +2645,17 @@ static void vd_proc_set(u32 vpp_index, struct vd_proc_s *vd_proc)
pr_info("%s: vd1_work_mode=%d, vd1_slices_dout_dpsel=%d, vd1_dout_hsize=%d, vd1_dout_vsize=%d\n",
__func__, vd1_work_mode, vd1_slices_dout_dpsel,
vd1_dout_hsize, vd1_dout_vsize);
if (vd_proc->vd1_used)
vd1_proc_set(vpp_index, vd_proc);
if (vd_proc->vd2_used)
vd2_proc_set(vpp_index, &vd_proc->vd2_proc);
if (vd_proc->vd_proc_preblend_info.vd1s0_vd2_prebld_en ||
vd_proc->vd_proc_preblend_info.vd1s1_vd2_prebld_en)
vd2_pre_blend_set(vpp_index, &vd_proc->vd_proc_preblend);
if (vd_proc->vd1_used && layer->layer_id == 0)
vd1_proc_set(layer, vd_proc);
if (vd_proc->vd2_used) {
if (vd_proc->vd_proc_preblend_info.vd1s1_vd2_prebld_en ||
vd_proc->vd_proc_preblend_info.vd1s0_vd2_prebld_en)
vd2_proc_set(get_vd_layer(1), &vd_proc->vd2_proc);
else
vd2_proc_set(layer, &vd_proc->vd2_proc);
}
vd2_pre_blend_set(vpp_index, &vd_proc->vd_proc_preblend);
/* path sel set */
switch (vd1_work_mode) {
@@ -3397,16 +3404,16 @@ static void set_vd_proc_info(struct video_layer_s *layer)
if (vd_proc->vd1_used &&
debug_flag_s5 & DEBUG_VD_PROC) {
pr_info("%s:vd_proc_vd1_info->slice_num=%d\n",
__func__, vd_proc_vd1_info->slice_num);
pr_info("%s:layer_id=%d vd_proc_vd1_info->slice_num=%d\n",
__func__, layer->layer_id, vd_proc_vd1_info->slice_num);
pr_info("%s:vd1_work_mode=0x%x, vd1_slices_dout_dpsel=0x%x, overlap=%d\n",
__func__, vd_proc_vd1_info->vd1_work_mode,
vd_proc_vd1_info->vd1_slices_dout_dpsel,
vd_proc_vd1_info->vd1_overlap_hsize);
} else if (vd_proc->vd2_used &&
debug_flag_s5 & DEBUG_VD2_PROC) {
pr_info("%s: vd2 used vpp_index=%d, vd2_dout_dpsel=%d, vd1s0_vd2_prebld_en=%d\n",
__func__, layer->vpp_index,
pr_info("%s: layer_id=%d vd2 used vpp_index=%d, vd2_dout_dpsel=%d, vd1s0_vd2_prebld_en=%d\n",
__func__, layer->layer_id, layer->vpp_index,
vd_proc_vd2_info->vd2_dout_dpsel,
vd_proc_preblend_info->vd1s0_vd2_prebld_en);
}
@@ -5716,10 +5723,11 @@ static void vd_proc_param_set(struct vd_proc_s *vd_proc, u32 frm_idx)
vd_proc->vd_proc_unit[1].reg_bypass_prebld = 1;
}
if (debug_flag_s5 & DEBUG_VD_PROC) {
pr_info("%s:reg_bypass_prebld: %d, %d\n",
pr_info("%s:reg_bypass_prebld: %d, %d, prebld bld_out_en=%d\n",
__func__,
vd_proc->vd_proc_unit[0].reg_bypass_prebld,
vd_proc->vd_proc_unit[1].reg_bypass_prebld);
vd_proc->vd_proc_unit[1].reg_bypass_prebld,
vd_proc->vd_proc_preblend.bld_out_en);
}
}
@@ -5945,7 +5953,7 @@ void vd_s5_hw_set(struct video_layer_s *layer,
/* update info for amvecm */
update_vd_proc_amvecm_info(vd_proc);
vd_proc_set(vpp_index, vd_proc);
vd_proc_set(layer, vd_proc);
if (layer->mosaic_mode) {
vd_mosaic_slices_padding_set(vpp_index, 0, vd_proc);
@@ -5963,7 +5971,7 @@ void vd_s5_hw_set(struct video_layer_s *layer,
// frame_par,
// dispbuf);
//_vd_fgrain_setting_s5(layer, dispbuf);
vd_proc_set(vpp_index, vd_proc);
vd_proc_set(layer, vd_proc);
vd_mosaic_slices_padding_set(vpp_index, 1, vd_proc);
/* set back to frame 0 */
vd_switch_frm_idx(vpp_index, 0);