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hdmitx: update s7d revb phy para [1/2]

Browse Source 
PD#SWPL-171664

Problem:
s7d reva eye-diagram CTS fail

Solution:
add post emphasis for clock channel to improve intra-pair skew

Verify:
ross

Test:
DRM-TX-78

Change-Id: I947dcffb66fb64bd19167ae7ee29311b53a8f1a5
Signed-off-by: zhou.han <zhou.han@amlogic.com>
This commit is contained in:
zhou.han
2024-06-27 15:46:38 +08:00
committed by gerrit autosubmit
parent 7ffea3b945
commit a5269dc628
1 changed files with 5 additions and 5 deletions
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drivers/media/vout/hdmitx21/hw/hw_s7d.c
+5 -5
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@@ -178,20 +178,20 @@ void set21_phy_by_mode_s7d(u32 mode)
case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
case HDMI_PHYPARA_4p5G:
case HDMI_PHYPARA_3p7G:
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x8003a8fb);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x1555);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x8003cafb);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x2555);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL3, 0x4ef001);
break;
case HDMI_PHYPARA_3G: /* 2.97Gbps */
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x800380dd);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x1555);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x2555);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL3, 0x4ef001);
break;
case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */
case HDMI_PHYPARA_DEF:
default:
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x820380a0);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x1555);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL0, 0x82038088);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL5, 0x2555);
hd21_write_reg(ANACTRL_HDMIPHY_CTRL3, 0x4ef001);
break;
}