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amvecm: 5.15 modify osd setting flow to match in/out csc type [1/1]

Browse Source 
PD#SWPL-149781

Problem:
modify osd setting flow

Solution:
modify osd setting flow

Verify:
t962d4

Change-Id: I3dd30d02767a85114682d130d2a5ce8ca22d78f6
Signed-off-by: jinbing.zhu <jinbing.zhu@amlogic.com>
This commit is contained in:
jinbing.zhu
2023-12-26 07:06:59 +00:00
committed by Luan Yuan
parent 0ec6dc100e
commit afc4a316fe
4 changed files with 55 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/enhancement/amvecm/amcsc.c
+10
View File
@@ -9765,4 +9765,14 @@ dbg_end:
return 0;
}
void get_source_csc_info(int vpp_index, int *source_type, int *csc_type)
{
if (!source_type || !csc_type)
return;
*source_type = get_source_type(VD1_PATH, vpp_index);
*csc_type = get_csc_type();
}
#endif
drivers/media/enhancement/amvecm/amcsc.h
+2
View File
@@ -322,5 +322,7 @@ int get_s5_slice_mode(void);
#define VD1_4SLICE 4
void pkt_delay_flag_init(void);
void get_source_csc_info(int vpp_index, int *source_type, int *csc_type);
#endif /* AM_CSC_H */
drivers/media/enhancement/amvecm/amcsc_pip.c
+19 -2
View File
@@ -156,17 +156,26 @@ static void hdr_proc(struct vframe_s *vf,
enum vpp_index_e vpp_index)
{
enum hdr_process_sel cur_hdr_process;
int limit_full = (vf->signal_type >> 25) & 0x01;
int limit_full = 0;
int i, index;
if (vf)
limit_full = (vf->signal_type >> 25) & 0x01;
pr_csc(128, "%s: module_sel = %d, limit_full = %d\n",
__func__, module_sel, limit_full);
/* RGB / YUV vdin input handling prepare extra op code or info */
if (vf->type & VIDTYPE_RGB_444 && !is_amdv_on())
if (vf && vf->type & VIDTYPE_RGB_444 && !is_amdv_on())
hdr_process_select |= RGB_VDIN;
if (limit_full && !is_amdv_on())
hdr_process_select |= FULL_VDIN;
/* RGB / YUV input handling */
pr_csc(128, "%s: hdr_process_select = 0x%08x\n",
__func__, hdr_process_select);
if (hdr_process_select & HDR10P_SDR)
cur_hdr_process =
hdr10p_func(module_sel, hdr_process_select, vinfo, gmt_mtx, vpp_index);
@@ -3358,6 +3367,8 @@ void video_post_process(struct vframe_s *vf,
vpp_index,
vinfo->mode,
__LINE__);
pr_csc(128, "%s: no lcd csc_type = %d\n",
__func__, csc_type);
if (vpp_index == VPP_TOP1)
mtx_setting(VPP1_POST2_MTX, MATRIX_NULL, MTX_OFF);
else if (vpp_index == VPP_TOP2)
@@ -3377,6 +3388,10 @@ void video_post_process(struct vframe_s *vf,
__func__,
vd_path + 1,
source_type[vd_path]);
pr_csc(128, "%s: sdr rgb444 csc_type = %d\n",
__func__, csc_type);
VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(VPP_VADJ1_MISC,
0, 1, 1, vpp_index);
VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(VPP_VADJ2_MISC,
@@ -3395,6 +3410,8 @@ void video_post_process(struct vframe_s *vf,
__func__,
vd_path + 1,
source_type[vd_path]);
pr_csc(128, "%s: others csc_type = %d\n",
__func__, csc_type);
/*VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 1, 1);*/
/*VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 1, 1);*/
VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(VPP_VADJ1_MISC,
drivers/media/enhancement/amvecm/set_hdr2_v0.c
+24 -1
View File
@@ -38,6 +38,7 @@
#include "hdr/am_cuva_hdr_tm.h"
#include <linux/amlogic/media/amvecm/cuva_alg.h>
#include "amve_v2.h"
#include "amcsc.h"
u32 disable_flush_flag;
module_param(disable_flush_flag, uint, 0664);
@@ -3023,6 +3024,9 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
int *oft_post_out = bypass_pos;
bool always_full_func = false;
int vpp_sel;
int cur_source;
int cur_csc;
#ifndef CONFIG_AMLOGIC_ZAPPER_CUT
enum LUT_DMA_ID_e dma_id = HDR_DMA_ID;
#endif
@@ -3081,7 +3085,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
return hdr_process_select;
}
pr_csc(12, "%s: hdr module=%d, proc sel=0x%x vpp_index = %d\n",
pr_csc(128, "%s: hdr module=%d, proc sel=0x%x vpp_index = %d\n",
__func__,
module_sel,
hdr_process_select,
@@ -3613,12 +3617,26 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
hdr_process_select & CUVAHLG_CUVA)) {
/* sdr process, always rgb osd here*/
if (hdr_process_select & RGB_OSD) {
pr_csc(128, "%s: RGB_OSD HDR_BYPASS, hdr_process_select = %x\n",
__func__, hdr_process_select);
pr_csc(128, "%s: RGB_OSD HDR_BYPASS, module_sel = %d\n",
__func__, module_sel);
if (hdr_process_select & RGB_VDIN) {
coeff_in = rgb2ycbcrf_709;
oft_pre_in = rgb2yuvfpre;
oft_post_in = rgb2yuvfpos;
oft_pre_out = bypass_pre;
oft_post_out = bypass_pos;
get_source_csc_info(vpp_index, &cur_source, &cur_csc);
pr_csc(128, "%s: RGB_OSD HDR_BYPASS, cur_source/csc = %d/%d\n",
__func__, cur_source, cur_csc);
if (cur_source != HDRTYPE_SDR &&
cur_csc != VPP_MATRIX_YUV709F_RGB) {
coeff_in = rgb2ycbcr_709;
oft_pre_in = rgb2yuvpre;
oft_post_in = rgb2yuvpos;
}
} else {
coeff_in = rgb2ycbcr_709;
oft_pre_in = rgb2yuvpre;
@@ -3627,6 +3645,7 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
oft_post_out = bypass_pos;
}
} else {
pr_csc(128, "%s: not RGB_OSD\n", __func__);
coeff_in = bypass_coeff;
oft_pre_in = bypass_pre;
oft_post_in = bypass_pos;
@@ -3641,6 +3660,8 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
hdr_process_select & SDR_IPT ||
hdr_process_select & CUVA_HDR ||
hdr_process_select & SDR_CUVA)) {
pr_csc(128, "%s: RGB_OSD, hdr_process_select = %x, module_sel = %d\n",
__func__, hdr_process_select, module_sel);
/* sdr process, always rgb osd here*/
if (hdr_process_select & RGB_OSD) {
coeff_in = bypass_coeff;
@@ -5017,6 +5038,8 @@ void mtx_setting(enum vpp_matrix_e mtx_sel,
matrix_en_ctrl = VPP2_POST2_MATRIX_EN_CTRL;
VSYNC_WRITE_VPP_REG_BITS_VPP_SEL(VPP2_POST2_MATRIX_EN_CTRL, mtx_on, 0, 1, vpp_sel);
} else {
return;
}
if (!mtx_on)