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https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
dsc dec: choose dsc pll as dsc clk [1/1]
PD#SWPL-239956 Problem: vpu clk div 2 unnormal. Solution: choose dsc pll as dsc clk. Verify: T6X Change-Id: I19017414876ac33601a6793e9a54fedaeb17e7c0 Signed-off-by: yaoyu.xu <yaoyu.xu@amlogic.com> (cherry picked from commit ff91423113b6fb002b3b4b5677a95d347c1fbd92)
This commit is contained in:
committed by
gerrit autosubmit
parent
7f95fe2d5e
commit
aff4c40127
@@ -7,11 +7,12 @@
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#include "dsc_dec_hw.h"
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#include "dsc_dec_debug.h"
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#include "dsc_dec_reg.h"
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#include "../tvin_global.h"
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#define MHz 1000000
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#define PIX_BAND0 (333 * MHz)
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#define PIX_BAND1 (370 * MHz)
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#define PIX_BAND2 (408 * MHz)
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#define PIX_BAND1 (358 * MHz)
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#define PIX_BAND2 (406 * MHz)
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#define VPU_CLK_DIV_2 1
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#define FPLL_DIV3 2
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@@ -946,6 +947,15 @@ void dsc_dec_clk_calculate(unsigned int integer, unsigned int frac)
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void dsc_clk_config(struct aml_dsc_dec_drv_s *dsc_dec_drv)
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{
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struct hdmi_dsc_pps_data_s *pps_data = &dsc_dec_drv->pps_data;
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u32 tmp;
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u32 clk;
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if (pps_data->native_420 == 1 || pps_data->native_422 == 1)
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tmp = 2;
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else
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tmp = 1;
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clk = pps_data->pixel_clk / (pps_data->bits_per_pixel / tmp) * 192;
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if (dsc_dec_drv->data->chip_type == DSC_DEC_CHIP_T3X) {
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dsc_dec_config_fix_pll_clk(DSC_CLK_BAND0);
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@@ -978,7 +988,7 @@ void dsc_clk_config(struct aml_dsc_dec_drv_s *dsc_dec_drv)
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}
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} else {
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if (pps_data->pic_width == 7680 && pps_data->pic_height == 4320) {
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set_dsc_clk_cntl(FPLL_DIV3);
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set_dsc_clk_cntl(FPLL_DIV3, clk);
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if (pps_data->pixel_clk <= PIX_BAND0) {
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//yuv420 ppc setting is different from others.
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if (dsc_dec_drv->pps_data.native_420)
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@@ -989,13 +999,20 @@ void dsc_clk_config(struct aml_dsc_dec_drv_s *dsc_dec_drv)
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dsc_dec_drv->pix_per_clk = 2;
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}
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} else {
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if ((pps_data->pixel_clk / pps_data->bits_per_pixel * 192 > PIX_BAND0) ||
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if (clk > PIX_BAND0 ||
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pps_data->dsc_force_4ppc) {
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dsc_dec_drv->pix_per_clk = 2;
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set_dsc_clk_cntl(VPU_CLK_DIV_2);
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if (clk <= PIX_BAND1)
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dsc_dec_config_fix_pll_clk(DSC_CLK_BAND1);
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else if (clk <= PIX_BAND2)
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dsc_dec_config_fix_pll_clk(DSC_CLK_BAND2);
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else
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dsc_dec_config_fix_pll_clk(DSC_CLK_BAND4);
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//need vpu clk enhance
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set_dsc_clk_cntl(DSC_PIX_PLL, clk);
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} else {
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dsc_dec_drv->pix_per_clk = 1;
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set_dsc_clk_cntl(FPLL_DIV3);
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set_dsc_clk_cntl(FPLL_DIV3, clk);
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}
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}
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}
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@@ -15,12 +15,13 @@
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#include "dsc_dec_debug.h"
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#include "dsc_dec_hw.h"
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const unsigned int ctrl0_vals[5][3] = {
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const unsigned int ctrl0_vals[6][3] = {
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[DSC_CLK_BAND0] = {0x20020cc6, 0x30020cc6, 0x10020cc6},
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[DSC_CLK_BAND1] = {0x2001083c, 0x3001083c, 0x1001083c},
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[DSC_CLK_BAND2] = {0x20010c88, 0x30010c88, 0x10010c88},
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[DSC_CLK_BAND3] = {0x20010cc6, 0x30010cc6, 0x10010cc6},
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[DSC_CLK_BAND4] = {0x20010c8c, 0x30010c8c, 0x10010c8c}
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[DSC_CLK_BAND4] = {0x20010c8f, 0x30010c8f, 0x10010c8f},
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[DSC_CLK_BAND5] = {0x20010844, 0x30010844, 0x10010844},
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};
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unsigned int R_DSC_DEC_CLKCTRL_REG(unsigned int reg)
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@@ -11,9 +11,10 @@
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enum dsc_clk_band {
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DSC_CLK_BAND0, //297M
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DSC_CLK_BAND1, //360M
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DSC_CLK_BAND2, //410M
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DSC_CLK_BAND3,//594M
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DSC_CLK_BAND4
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DSC_CLK_BAND2, //408M
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DSC_CLK_BAND3, //594M
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DSC_CLK_BAND4, //429M
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DSC_CLK_BAND5, //408M
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};
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unsigned int R_DSC_DEC_CLKCTRL_REG(unsigned int reg);
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@@ -29,6 +29,8 @@
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#include <linux/io.h>
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#include <linux/compat.h>
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#include <linux/suspend.h>
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#include <linux/amlogic/media/vpu/vpu.h>
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/* #include <linux/earlysuspend.h> */
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#include <linux/delay.h>
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#include <linux/of.h>
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@@ -124,6 +126,8 @@ struct work_struct clkmsr_dwork;
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struct workqueue_struct *clkmsr_wq;
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struct work_struct earc_hpd_dwork;
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struct workqueue_struct *earc_hpd_wq;
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struct work_struct vpu_dwork;
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struct workqueue_struct *vpu_wq;
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struct edid_delayed_work_data edid_reset_work;
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// edid updata
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@@ -634,6 +638,8 @@ void hdmirx_dec_stop(struct tvin_frontend_s *fe, enum tvin_port_e port,
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/* parm->info.fmt = TVIN_SIG_FMT_NULL; */
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/* parm->info.status = TVIN_SIG_STATUS_NULL; */
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rx_pr("%s port:%d, port_type:%d ok\n", __func__, port - TVIN_PORT_HDMI0, port_type);
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if (rx_info.chip_id == CHIP_ID_T6X)
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rx_switch_vpu_clk(0);
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}
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/*
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@@ -1738,7 +1744,10 @@ void hdmirx_get_spd_info(struct tvin_frontend_s *fe,
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port = rx_get_port_from_type(port_type);
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memcpy(&prop->spd_data, &rx_pkt[port].spd_info, sizeof(struct tvin_spd_data_s));
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}
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void __weak dsc_update_vstart(int vstart, int vend, int odd)
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{
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}
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void hdmirx_get_pps_info(struct tvin_sig_property_s *prop, u8 port)//todo)
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@@ -4590,6 +4599,9 @@ static int hdmirx_probe(struct platform_device *pdev)
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earc_hpd_wq = create_workqueue(hdevp->frontend.name);
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INIT_WORK(&earc_hpd_dwork, rx_earc_hpd_handler);
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vpu_wq = create_workqueue(hdevp->frontend.name);
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INIT_WORK(&vpu_dwork, rx_vpu_handler);
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INIT_DELAYED_WORK(&edid_reset_work.delayed_work, rx_edid_reset_handler);
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/* create for frl training */
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kthread_init_worker(&frl_worker);
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@@ -1217,6 +1217,9 @@ extern struct workqueue_struct *clkmsr_wq;
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extern struct edid_delayed_work_data edid_reset_work;
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extern struct work_struct earc_hpd_dwork;
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extern struct workqueue_struct *earc_hpd_wq;
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extern struct work_struct vpu_dwork;
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extern struct workqueue_struct *vpu_wq;
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extern struct workqueue_struct *repeater_wq;
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extern struct edid_update_work_s edid_update_dwork;
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extern struct workqueue_struct *edid_update_wq;
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@@ -29,6 +29,8 @@
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#include <linux/amlogic/clk_measure.h>
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#include <linux/amlogic/media/video_sink/video.h>
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#include <uapi/amlogic/hdmi_rx.h>
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#include "../tvin_global.h"
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/* Local Include */
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#include "hdmi_rx_repeater.h"
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#include "hdmi_rx_drv.h"
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@@ -1271,10 +1273,12 @@ void rx_set_dsc_hdmi_cntl(unsigned int val)
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hdmirx_wr_top_common(TOP_DSC_HDMI_CNTL, val);
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}
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void set_dsc_clk_cntl(int clk_select)
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void set_dsc_clk_cntl(int clk_select, int clk)
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{
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if (rx_info.chip_id != CHIP_ID_T6X)
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return;
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if (clk >= 406 * MHz && clk_select == H_DSC_PIX_PLL)
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schedule_work(&vpu_dwork);
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if (clk_select == H_VPU_CLK_DIV_2)
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wr_reg_clk_ctl(CLKCTRL_DSC_CLK_CTRL, 0x343);
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else if (clk_select == H_FPLL_DIV3)
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@@ -30,6 +30,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/highmem.h>
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#include <linux/amlogic/clk_measure.h>
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#include <linux/amlogic/media/vpu/vpu.h>
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/* Local include */
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#include "hdmi_rx_eq.h"
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@@ -8997,3 +8998,9 @@ void hdmi_rx_cor_reset(u8 port)
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udelay(1);
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hdmirx_wr_top(TOP_SW_RESET, 0, port);
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}
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void rx_vpu_handler(struct work_struct *work)
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{
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rx_switch_vpu_clk(1);
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}
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@@ -3799,4 +3799,6 @@ bool hdmi_rx_is_fifo_unnormal(u8 port);
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void hdmi_rx_frl_pix_chg(u8 port);
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u32 hdmirx_rd_ee_vol(u32 addr);
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void hdmirx_wr_ee_vol(u32 addr, u32 data);
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void rx_vpu_handler(struct work_struct *work);
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#endif
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@@ -28,6 +28,7 @@
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#include <linux/sched/clock.h>
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#include <linux/amlogic/clk_measure.h>
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#include <linux/hrtimer.h>
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#include <linux/amlogic/media/vpu/vpu.h>
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/* Local include */
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#include "hdmi_rx_repeater.h"
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@@ -4281,6 +4282,11 @@ void wait_ddc_idle(u8 port)
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}
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}
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unsigned int __weak rx_switch_vpu_clk(int over_clock_flag)
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{
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return 0;
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}
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void hdmirx_open_main_port_t3x(u8 port)
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{
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if (rx_info.main_port_open && port == rx_info.main_port)
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@@ -4405,6 +4411,8 @@ void hdmirx_close_port_t3x(u8 port)
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}
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rx_emp_hw_enable(false);
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rx_irq_en(0, port);
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if (rx_info.chip_id == CHIP_ID_T6X)
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rx_switch_vpu_clk(0);
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}
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void hdmirx_close_port(u8 port)
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@@ -225,6 +225,8 @@ void rx_edid_update_handler(struct work_struct *dwork);
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void frate_monitor(void);
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void frate_monitor1(void);
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unsigned int rx_switch_vpu_clk(int over_clock_flag);
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void __weak set_video_mute(u32 owner, bool on)
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{
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}
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@@ -618,8 +618,5 @@ struct tvin_sig_property_s {
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#define BT656IN_ANCI_DATA_SIZE 0x4000 /* save anci data from bt656in */
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#define CAMERA_IN_ANCI_DATA_SIZE 0x4000 /* save anci data from bt656in */
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void dsc_update_vstart(int vstart, int vend, int odd);
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void __weak dsc_update_vstart(int vstart, int vend, int odd)
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{
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}
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void set_dsc_clk_cntl(int clk_select, int clk);
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#endif /* __TVIN_GLOBAL_H */
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@@ -262,7 +262,6 @@ struct hdmirx_scdc_info {
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#define HDMI_IOC_AUDIO_DATA_DUMP _IO(HDMI_IOC_MAGIC, 0x1b)
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void rx_set_dsc_hdmi_cntl(unsigned int val);
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void set_dsc_clk_cntl(int clk_select);
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#endif
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