shinys000114/kernel_common_drivers
1
0
Fork 0
mirror of https://github.com/hardkernel/kernel_common_drivers.git synced 2026-06-25 12:03:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm: change afbc format [1/1]

Browse Source 
PD#SWPL-163150

Problem:
support DRM_FORMAT_ABGR1010102

Solution:
support DRM_FORMAT_ABGR1010102

Verify:
S7D

Test:
DRM-OSD-6

Change-Id: I20a2b0080dd99baafd9fff4b0c6a9a32a99df58a
Signed-off-by: wenlong.zhang <wenlong.zhang@amlogic.com>
This commit is contained in:
wenlong.zhang
2024-04-08 02:55:46 +00:00
committed by yao zhang1
parent a8a5147363
commit b3436bfa11
4 changed files with 6 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/drm/meson_fb.c
+1 -1
View File
@@ -9,7 +9,7 @@
#include "meson_vpu.h"
static const struct drm_format_info meson_formats[] = {
{ .format = DRM_FORMAT_RGBA10101010, .depth = 40, .num_planes = 1,
{ .format = DRM_FORMAT_ABGR10101010, .depth = 40, .num_planes = 1,
.cpp = { 5, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
};
drivers/drm/meson_plane.c
+2 -6
View File
@@ -158,11 +158,8 @@ u32 supported_drm_formats_v4[] = {
/* default groups + 10101010 format for s7d*/
u32 supported_drm_formats_v5[] = {
DRM_FORMAT_RGBA10101010,
DRM_FORMAT_RGBA1010102,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_ABGR10101010,
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_BGRA1010102,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_RGBX8888,
@@ -1030,8 +1027,7 @@ bool am_meson_vpu_check_format_mod(struct drm_plane *plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_RGBA10101010:
case DRM_FORMAT_RGBA1010102:
case DRM_FORMAT_ABGR10101010:
case DRM_FORMAT_RGBA8888:
return true;
case DRM_FORMAT_RGB888:
drivers/drm/vpu-hw/meson_vpu_osd_mif.c
+2 -2
View File
@@ -642,7 +642,7 @@ const struct meson_drm_format_info *__meson_drm_gfcd_format_info(u32 format)
.gfcd_hw_blkmode_afbc = GFCD_AFBC_BLOCK_MODE_RGBA8888,
.gfcd_hw_blkmode_afrc = GFCD_AFRC_BLOCK_MODE_RGBA8888,
.alpha_replace = 0 },
{ .format = DRM_FORMAT_RGBA1010102,
{ .format = DRM_FORMAT_ABGR2101010,
.gfcd_hw_blkmode_afbc = GFCD_AFBC_BLOCK_MODE_RGBA1010102,
.gfcd_hw_blkmode_afrc = BLOCK_MODE_RESERVED,
.alpha_replace = 0 },
@@ -650,7 +650,7 @@ const struct meson_drm_format_info *__meson_drm_gfcd_format_info(u32 format)
.gfcd_hw_blkmode_afbc = GFCD_AFBC_BLOCK_MODE_RGB888,
.gfcd_hw_blkmode_afrc = BLOCK_MODE_RESERVED,
.alpha_replace = 1 },
{ .format = DRM_FORMAT_RGBA10101010,
{ .format = DRM_FORMAT_ABGR10101010,
.gfcd_hw_blkmode_afbc = GFCD_AFBC_BLOCK_MODE_RGBA10101010,
.gfcd_hw_blkmode_afrc = GFCD_AFRC_BLOCK_MODE_RGBA10101010,
.alpha_replace = 0 },
include/uapi/amlogic/drm/meson_drm.h
+1 -1
View File
@@ -28,7 +28,7 @@
#define MAX_VRR_MODE_GROUP 12
/* 40 bpp RGB */
#define DRM_FORMAT_RGBA10101010 fourcc_code('A', 'B', '4', '0')
#define DRM_FORMAT_ABGR10101010 fourcc_code('A', 'B', '4', '0')
/* [39:0] A:B:G:R 10:10:10:10 little endian */
/**