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dtv_demod: fix t5m dvbc 128qam unlock(V1.1.87) [1/1]
PD#SWPL-110993 Problem: t5m dvbc 128qam unlock. Solution: 1.fix t5m dvbc 128qam unlock. 2.AMLDTVDEMOD_VER "V1.1.87". Verify: verify by T5M. Change-Id: I3177c90a74d70017c68ba055410c5d7fdc952bae Signed-off-by: zhicheng.huang <zhicheng.huang@amlogic.com>
This commit is contained in:
zhicheng.huang
committed by
gerrit autosubmit
gerrit autosubmit
parent
e9d1b749fa
commit
b4adc46e9c
@@ -777,8 +777,11 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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unsigned int idx_1_acc = 0, idx_2_acc = 0, idx_4_acc = 0;
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unsigned int idx_8_acc = 0, idx_16_acc = 0, idx_32_acc = 0;
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unsigned int idx_64_acc = 0, idx_128_acc = 0, idx_256_acc = 0;
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unsigned int idx_00 = 0, idx_77 = 0, idx_all = 0;
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unsigned int be = 0, bf = 0, c0 = 0, d3 = 0, d4 = 0, d5 = 0;
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unsigned int idx[64] = { 0 }, idx_77 = 0, idx_all = 0;
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unsigned int be = 0, bf = 0, c0 = 0, c1 = 0, c2 = 0, c3 = 0, c4 = 0;
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unsigned int c5 = 0, c6 = 0, c7 = 0, c8 = 0, c9 = 0, ca = 0, cb = 0;
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unsigned int cc = 0, cd = 0, ce = 0, cf = 0, d0 = 0, d1 = 0, d2 = 0;
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unsigned int d3 = 0, d4 = 0, d5 = 0;
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unsigned int aa = 0, bb = 0;
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unsigned int lock_flag = 0, eq_state = 0;
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unsigned int find_qam = 0xf;
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@@ -796,15 +799,46 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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}
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// 2. get QAM constellation map accumulated value.
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be = qam_read_reg(demod, 0xbe);
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bf = qam_read_reg(demod, 0xbf);
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c0 = qam_read_reg(demod, 0xc0);
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if (!is_meson_t5m_cpu()) {
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be = qam_read_reg(demod, 0xbe);
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bf = qam_read_reg(demod, 0xbf);
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c0 = qam_read_reg(demod, 0xc0);
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}
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if (eq_state > 0x01) {
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// 3. get QAM probability distribution.
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d4 = qam_read_reg(demod, 0xd4);
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d5 = qam_read_reg(demod, 0xd5);
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d3 = qam_read_reg(demod, 0xd3);
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if (!is_meson_t5m_cpu()) {
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d4 = qam_read_reg(demod, 0xd4);
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d5 = qam_read_reg(demod, 0xd5);
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d3 = qam_read_reg(demod, 0xd3);
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}
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if (is_meson_t5m_cpu()) {
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be = qam_read_reg(demod, 0xbe);
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bf = qam_read_reg(demod, 0xbf);
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c0 = qam_read_reg(demod, 0xc0);
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c1 = qam_read_reg(demod, 0xc1);
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c2 = qam_read_reg(demod, 0xc2);
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c3 = qam_read_reg(demod, 0xc3);
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c4 = qam_read_reg(demod, 0xc4);
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c5 = qam_read_reg(demod, 0xc5);
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c6 = qam_read_reg(demod, 0xc6);
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c7 = qam_read_reg(demod, 0xc7);
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c8 = qam_read_reg(demod, 0xc8);
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c9 = qam_read_reg(demod, 0xc9);
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ca = qam_read_reg(demod, 0xca);
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cb = qam_read_reg(demod, 0xcb);
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cc = qam_read_reg(demod, 0xcc);
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cd = qam_read_reg(demod, 0xcd);
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ce = qam_read_reg(demod, 0xce);
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cf = qam_read_reg(demod, 0xcf);
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d0 = qam_read_reg(demod, 0xd0);
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d1 = qam_read_reg(demod, 0xd1);
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d2 = qam_read_reg(demod, 0xd2);
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d3 = qam_read_reg(demod, 0xd3);
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d4 = qam_read_reg(demod, 0xd4);
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d5 = qam_read_reg(demod, 0xd5);
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}
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PR_DVBC("%s: 0xbe[0x%x], 0xbf[0x%x], 0xc0[0x%x].\n",
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__func__, be, bf, c0);
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@@ -812,17 +846,80 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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__func__, d3, d4, d5);
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if (is_meson_t5m_cpu()) {
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idx_00 = be & 0x1ff;
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idx[0] = be & 0x1ff;
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idx[1] = (be >> 10) & 0x1ff;
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idx[2] = (be >> 20) & 0x1ff;
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idx[3] = bf & 0x1ff;
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idx[4] = (bf >> 10) & 0x1ff;
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idx[5] = (bf >> 20) & 0x1ff;
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idx[6] = c0 & 0x1ff;
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idx[7] = (c0 >> 10) & 0x1ff;
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idx[8] = (c0 >> 20) & 0x1ff;
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idx[9] = c1 & 0x1ff;
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idx[10] = (c1 >> 10) & 0x1ff;
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idx[11] = (c1 >> 20) & 0x1ff;
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idx[12] = c2 & 0x1ff;
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idx[13] = (c2 >> 10) & 0x1ff;
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idx[14] = (c2 >> 20) & 0x1ff;
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idx[15] = c3 & 0x1ff;
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idx[16] = (c3 >> 10) & 0x1ff;
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idx[17] = (c3 >> 20) & 0x1ff;
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idx[18] = c4 & 0x1ff;
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idx[19] = (c4 >> 10) & 0x1ff;
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idx[20] = (c4 >> 20) & 0x1ff;
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idx[21] = c5 & 0x1ff;
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idx[22] = (c5 >> 10) & 0x1ff;
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idx[23] = (c5 >> 20) & 0x1ff;
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idx[24] = c6 & 0x1ff;
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idx[25] = (c6 >> 10) & 0x1ff;
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idx[26] = (c6 >> 20) & 0x1ff;
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idx[27] = c7 & 0x1ff;
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idx[28] = (c7 >> 10) & 0x1ff;
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idx[29] = (c7 >> 20) & 0x1ff;
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idx[30] = c8 & 0x1ff;
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idx[31] = (c8 >> 10) & 0x1ff;
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idx[32] = (c8 >> 20) & 0x1ff;
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idx[33] = c9 & 0x1ff;
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idx[34] = (c9 >> 10) & 0x1ff;
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idx[35] = (c9 >> 20) & 0x1ff;
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idx[36] = ca & 0x1ff;
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idx[37] = (ca >> 10) & 0x1ff;
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idx[38] = (ca >> 20) & 0x1ff;
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idx[39] = cb & 0x1ff;
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idx[40] = (cb >> 10) & 0x1ff;
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idx[41] = (cb >> 20) & 0x1ff;
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idx[42] = cc & 0x1ff;
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idx[43] = (cc >> 10) & 0x1ff;
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idx[44] = (cc >> 20) & 0x1ff;
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idx[45] = cd & 0x1ff;
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idx[46] = (cd >> 10) & 0x1ff;
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idx[47] = (cd >> 20) & 0x1ff;
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idx[48] = ce & 0x1ff;
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idx[49] = (ce >> 10) & 0x1ff;
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idx[50] = (ce >> 20) & 0x1ff;
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idx[51] = cf & 0x1ff;
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idx[52] = (cf >> 10) & 0x1ff;
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idx[53] = (cf >> 20) & 0x1ff;
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idx[54] = d0 & 0x1ff;
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idx[55] = (d0 >> 10) & 0x1ff;
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idx[56] = (d0 >> 20) & 0x1ff;
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idx[57] = d1 & 0x1ff;
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idx[58] = (d1 >> 10) & 0x1ff;
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idx[59] = (d1 >> 20) & 0x1ff;
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idx[60] = d2 & 0x1ff;
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idx[61] = (d2 >> 10) & 0x1ff;
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idx[62] = (d2 >> 20) & 0x1ff;
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idx[63] = d3 & 0x1ff;
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} else {
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idx_00 = (be & 0x1);
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idx_00 += ((be >> 2) & 0x1) * 2;
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idx_00 += ((be >> 4) & 0x1) * 4;
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idx_00 += (bf & 0x1) * 8;
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idx_00 += ((bf >> 2) & 0x1) * 16;
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idx_00 += ((bf >> 4) & 0x1) * 32;
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idx_00 += (c0 & 0x1) * 64;
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idx_00 += ((c0 >> 2) & 0x1) * 128;
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idx_00 += ((c0 >> 4) & 0x1) * 256;
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idx[0] = (be & 0x1);
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idx[0] += ((be >> 2) & 0x1) * 2;
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idx[0] += ((be >> 4) & 0x1) * 4;
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idx[0] += (bf & 0x1) * 8;
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idx[0] += ((bf >> 2) & 0x1) * 16;
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idx[0] += ((bf >> 4) & 0x1) * 32;
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idx[0] += (c0 & 0x1) * 64;
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idx[0] += ((c0 >> 2) & 0x1) * 128;
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idx[0] += ((c0 >> 4) & 0x1) * 256;
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}
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idx_2_acc = d4 & 0x7f;
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@@ -846,8 +943,8 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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total_64_128_256_acc = idx_64_acc + idx_128_acc + idx_256_acc;
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PR_DVBC("%s: idx_00[0x%x], idx_77[0x%x].\n",
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__func__, idx_00, idx_77);
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PR_DVBC("%s: idx[0][0x%x], idx_77[0x%x].\n",
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__func__, idx[0], idx_77);
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PR_DVBC("%s: idx_1_acc[0x%x], idx_2_acc[0x%x], idx_4_acc[0x%x].\n",
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__func__, idx_1_acc, idx_2_acc, idx_4_acc);
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PR_DVBC("%s: idx_8_acc[0x%x], idx_16_acc[0x%x], index_32_acc[0x%x].\n",
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@@ -858,7 +955,10 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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__func__, total_64_128_256_acc);
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if (is_meson_t5m_cpu()) {
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idx_all = d3 & 0x1ff;
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for (i = 0; i < 64; ++i)
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idx_all += idx[i];
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idx_all = idx_all >> 6;
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} else {
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idx_all = idx_256_acc * 256;
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idx_all += idx_128_acc * 128;
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@@ -869,7 +969,7 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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idx_all += idx_4_acc * 4;
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idx_all += idx_2_acc * 2;
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idx_all += idx_1_acc;
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idx_all += idx_00;
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idx_all += idx[0];
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idx_all = idx_all >> 6;
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}
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@@ -898,15 +998,30 @@ unsigned int dvbc_auto_qam_process(struct aml_dtvdemod *demod)
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__func__, lock_flag, aa, bb);
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// 5. get qam.
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if (bb >= 60 && total_64_128_256_acc > 4) {
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if (idx_77 < 2000) {
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find_qam = QAM_MODE_128;
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if (idx_00 <= 24 || idx_256_acc < 40)
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if (is_meson_t5m_cpu()) {
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if (bb >= 60 && total_64_128_256_acc > 4) {
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if (lock_flag == 1 || idx_77 > 5000)
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find_qam = QAM_MODE_256;
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else if ((idx_77 > 2500) && (idx[0] > 24))
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find_qam = QAM_MODE_64;
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else if ((idx_77 < 2500) && (idx[0] > 24))
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find_qam = QAM_MODE_128;
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else if ((idx[0] <= 24) && (idx_77 < 2500))
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find_qam = QAM_MODE_32;
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} else if ((lock_flag == 1) || (idx_77 > 2000)) {
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find_qam = QAM_MODE_256;
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} else {
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find_qam = QAM_MODE_16;
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else
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find_qam = QAM_MODE_16;
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}
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} else {
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if (bb >= 60 && total_64_128_256_acc > 4) {
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if (idx_77 < 2000) {
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find_qam = QAM_MODE_128;
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if (idx[0] <= 24 || idx_256_acc < 40)
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find_qam = QAM_MODE_32;
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} else if ((lock_flag == 1) || (idx_77 > 2000)) {
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find_qam = QAM_MODE_256;
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} else {
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find_qam = QAM_MODE_16;
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}
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}
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}
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}
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@@ -78,6 +78,7 @@
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/* V1.1.84 rebuild isdbt to improve signal locking performance */
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/* V1.1.85 change the calculation method of ber */
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/* V1.1.86 remove S/S2 ber config */
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/* V1.1.87 fix t5m dvbc 128qam unlock */
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/****************************************************/
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/****************************************************************/
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/* AMLDTVDEMOD_VER Description: */
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@@ -94,8 +95,8 @@
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/*->The last four digits indicate the release time */
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/****************************************************************/
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#define KERNEL_4_9_EN 1
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#define AMLDTVDEMOD_VER "V1.1.86"
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#define DTVDEMOD_VER "2023/3/8: remove S/S2 ber config"
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#define AMLDTVDEMOD_VER "V1.1.87"
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#define DTVDEMOD_VER "2023/3/13: fix t5m dvbc 128qam unlock"
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#define AMLDTVDEMOD_T2_FW_VER "V1551.20220524"
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#define DEMOD_DEVICE_NAME "dtvdemod"
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