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vpu: modify vpu clk level to 8 [1/1]

Browse Source 
PD#SWPL-173011

Problem:
modify vpu clk level to 8

Solution:
complete it

Verify:
s6

Change-Id: Ibcb6e19747beedcd4c3dbbb54691c791ab2735e1
Signed-off-by: yuhua.lin <yuhua.lin@amlogic.com>
This commit is contained in:
yuhua.lin
2024-06-15 15:37:09 +08:00
committed by Luan Yuan
parent 6f6eaea358
commit bbaeb61cd3
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-s6.dtsi
+3 -3
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@@ -1840,9 +1840,9 @@
"vpu_clk0",
"vpu_clk1",
"vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
clk_level = <8>;
/* 0: 24.0M 1: 100.0M 2: 166.7M 3: 200.0M 4: 250.0M */
/* 5: 333.3M 6: 400.0M 7: 500.0M 8: 666.7M */
};
rdma {