amdv: L1L4 enable case5350/5354/5355 [1/1]

PD#SWPL-136154

Problem:
cmodel hist has delay, not match board

Solution:
In cert mode,add hist delay to match cmodel

Verify:
t3x

Change-Id: I7c2dc8fdca4e3ca456f93636fb24cd35ade26ba0
Signed-off-by: yao liu <yao.liu@amlogic.com>

drivers/media/enhancement/amdolby_vision/amdv.c

@@ -1808,6 +1808,11 @@ void set_frame_count(int val)
 {
 	if (!multi_dv_mode)
 		frame_count = val;
+
+	if (is_aml_hw5()) {
+		top1_v_info.frame_count = 0;
+		top2_v_info.frame_count = 0;
+	}
 }
 
 int get_frame_count(void)
@@ -1877,6 +1882,7 @@ void reset_dv_param(void)
 		top2_v_info.frame_count = 0;
 		py_wr_id = 0;
 		py_rd_id = 0;
+		l1l4_distance = 0;
 		memset(&dv5_md_hist.hist[0], 0, sizeof(dv5_md_hist.hist));
 		memset(&dv5_md_hist.l1l4_md[0], 0, sizeof(dv5_md_hist.l1l4_md));
 		memset(dv5_md_hist.hist_vaddr[0], 0, dv5_md_hist.hist_size);
@@ -16017,9 +16023,10 @@ static ssize_t amdolby_vision_inst_status_show
 			tv_hw5_setting->pq_config->tdc.pr_config.precision_rendering_strength,
 			tv_hw5_setting->pq_config->tdc.ana_config.enalbe_l1l4_gen);
 		}
-		len += sprintf(buf + len, "pyramid:wr=%d rd=%d level=%s,cfg enabled=%d\n",
+		len += sprintf(buf + len, "pyramid:wr=%d rd=%d level=%s,pd=%d,l1l4=%d %d\n",
 			py_wr_id, py_rd_id,
-			py_level == 0 ? "6" : (py_level == 1 ? "7" : "0"), py_enabled);
+			py_level == 0 ? "6" : (py_level == 1 ? "7" : "0"),
+			py_enabled, l1l4_enabled, l1l4_distance);
 
 		len += sprintf(buf + len, "==========TOP1=========\n");
 		len += sprintf(buf + len, "top1 enable: %d\n", enable_top1);

drivers/media/enhancement/amdolby_vision/amdv.h

@@ -894,6 +894,8 @@ extern u32 content_fps;
 extern u32 num_downsamplers;
 extern u32 force_sdr10;
 extern bool py_enabled;
+extern bool l1l4_enabled;
+extern u32 l1l4_distance;
 extern u8 force_drm[32];
 extern bool dv_unique_drm;
 /************/

drivers/media/enhancement/amdolby_vision/amdv_hw5.c

@@ -67,7 +67,8 @@ static int last_int_top2 = 0x10;/*bit4 out_frm_wr_done*/
 static u32 last_py_level = NO_LEVEL;
 u32 py_level = NO_LEVEL;/*todo*/
 bool py_enabled = true;/*when top1 on,enable pyramid by default.some idk case disable pyramid*/
-
+bool l1l4_enabled = true;/*when top1 on,enable l1l4 by default.some idk case disable l1l4*/
+u32 l1l4_distance;
 struct vd_proc_info_t *vd_proc_info;
 
 u32 test_dv;
@@ -390,8 +391,10 @@ static void dolby5_top1_rdmif
 static void check_pr_enabled(void)
 {
 	bool pr_enabled = true;
+	bool l1l4 = true;
 
 	if (tv_hw5_setting && tv_hw5_setting->pq_config) {
+		l1l4 = tv_hw5_setting->pq_config->tdc.ana_config.enalbe_l1l4_gen;
 		pr_enabled = tv_hw5_setting->pq_config->tdc.pr_config.supports_precision_rendering;
 
 		if (pr_enabled && tv_hw5_setting->dynamic_cfg)
@@ -403,6 +406,13 @@ static void check_pr_enabled(void)
 		pr_dv_dbg("top1 enabled but pyramid disabled!\n");
 
 	py_enabled = pr_enabled;
+	l1l4_enabled = l1l4;
+	if (!l1l4_enabled)
+		l1l4_distance = 0;
+	else if (py_enabled)
+		l1l4_distance = 1;
+	else
+		l1l4_distance = 2;
 }
 
 /*if pyramid is enable in cfg, we force enable pyramid for top1+top1b due to*/
@@ -1032,6 +1042,8 @@ void enable_amdv_hw5(int enable)
 				if (dolby_vision_flags & FLAG_BYPASS_VPP)
 					video_effect_bypass(1);
 			}
+			isr_cnt = 0;
+			top1_done = false;
 			pr_info("TV core turn on\n");
 		} else {
 			if (!top1_info.core_on && enable_top1 &&
@@ -1695,6 +1707,8 @@ int tv_top_set(u64 *top1_reg,
 			py_rd_id = 0;
 			l1l4_rd_index = 0;
 			l1l4_wr_index = 0;
+			isr_cnt = 0;
+			top1_done = false;
 		}
 
 		/*update pyramid write index when toggle new frame, except first frame*/
@@ -1714,6 +1728,8 @@ int tv_top_set(u64 *top1_reg,
 	} else {
 		top1_info.core_on = false;
 		top1_info.core_on_cnt = 0;
+		if (!top2_info.core_on)
+			isr_cnt = 0;
 	}
 
 	/*first frame with top1, not enable top2*/
@@ -1840,9 +1856,15 @@ void get_l1l4_hist(void)
 	tv_hw5_setting->top1_stats.top1_l1l4.l4_std = dv5_md_hist.l1l4_md[index][3];
 
 	if (debug_dolby & 0x100000)
-		pr_info("get hist[%d], index %d %d\n", index, l1l4_rd_index, l1l4_wr_index);
+		pr_info("get hist[%d], index %d/%d, l1l4_distance %d\n",
+			index, l1l4_rd_index, l1l4_wr_index, l1l4_distance);
 
-	l1l4_rd_index = l1l4_rd_index ^ 1;
+	if (dolby_vision_flags & FLAG_CERTIFICATION) {
+		if (top2_info.core_on_cnt >= l1l4_distance)/*cmodel hist delay one or two frame*/
+			l1l4_rd_index = (l1l4_rd_index + 1) % HIST_BUF_COUNT;
+	} else {
+		l1l4_rd_index = (l1l4_rd_index + 1) % HIST_BUF_COUNT;
+	}
 }
 
 #define FOR_DEBUG 0
@@ -1867,7 +1889,7 @@ void set_l1l4_hist(void)
 	if (new_top1_toggle) {
 		new_top1_toggle = false;
 		if (top1_info.core_on_cnt > 1)
-			l1l4_wr_index = l1l4_wr_index ^ 1;
+			l1l4_wr_index = (l1l4_wr_index + 1) % HIST_BUF_COUNT;
 	}
 
 	index = l1l4_wr_index;

drivers/media/enhancement/amdolby_vision/amdv_hw5.h

@@ -11,13 +11,15 @@
 
 #include <linux/types.h>
 
+#define HIST_BUF_COUNT 3
+
 struct dolby5_top1_md_hist {
-	u32 l1l4_md[2][4];
+	u32 l1l4_md[HIST_BUF_COUNT][4];
 	u8 hist[256];
 	void *hist_vaddr[2];
 	dma_addr_t hist_paddr[2];
 	u32 hist_size;
-	u16 histogram[2][128];
+	u16 histogram[HIST_BUF_COUNT][128];
 };
 
 struct dolby5_top1_type {