mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
hdmirx: i2c monitor [1/1]
PD#SWPL-132152 Problem: support to dump i2c data Solution: support to dump i2c data Verify: t3x Change-Id: I127e91f84297daddee6b720eba2bff17f53104e2 Signed-off-by: Gaowei Zhao <gaowei.zhao@amlogic.com>
This commit is contained in:
Gaowei Zhao
committed by
gerrit autosubmit
gerrit autosubmit
parent
2bab1d3389
commit
c19d943134
@@ -628,7 +628,7 @@
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0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0
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0x0 0xfe390000 0x0 0x20000
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0x0 0xfe000000 0x0 0x1fff
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0x0 0xfe000000 0x0 0x15000
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0x0 0xfe008000 0x280 0x334>;
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};
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@@ -770,6 +770,11 @@ struct emp_info_s {
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u8 data_ver;
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};
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struct i2c_info_s {
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phys_addr_t phy_addr;
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struct page *pg_addr;
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};
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struct spkts_rcvd_sts {
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u32 pkt_vsi_rcvd:1;
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u32 pkt_drm_rcvd:1;
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@@ -840,6 +845,7 @@ struct rx_info_s {
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struct rx_aml_phy aml_phy_21;
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struct emp_info_s emp_buff_a; //for vid0
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struct emp_info_s emp_buff_b; //for vid1
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struct i2c_info_s i2c_buff;
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struct edid_capacity edid_cap;
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bool suspend_flag;
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};
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@@ -6026,6 +6026,9 @@ int rx_debug_wr_reg(const char *buf, char *tmpbuf, int i, u8 port)
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} else if (buf[2] == 'A') {
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hdmirx_wr_amlphy_t3x(adr, value, port);
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rx_pr("write %x to port%d [%x]\n", value, port, adr);
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} else if (buf[2] == 'c') {
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wr_reg_clk_ctl(adr, value);
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rx_pr("write %x to [%x]\n", value, adr);
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}
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}
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return 0;
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@@ -6072,6 +6075,9 @@ int rx_debug_rd_reg(const char *buf, char *tmpbuf, u8 port)
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} else if (buf[2] == 'A') {
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value = hdmirx_rd_amlphy_t3x(adr, port);
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rx_pr("port%d, amlphy [%x]=%x\n", port, adr, value);
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} else if (buf[2] == 'c') {
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value = rd_reg_clk_ctl(adr);
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rx_pr("amlphy [%x]=%x\n", adr, value);
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}
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}
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return 0;
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@@ -3430,6 +3430,7 @@ unsigned int hdmirx_rd_amlphy(unsigned int addr);
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unsigned int hdmirx_rd_amlphy_t3x(unsigned int addr, u8 port);
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void hdmirx_irq_hdcp_enable(bool enable, u8 port);
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u8 rx_get_avmute_sts(u8 port);
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void wr_reg_ana_ctl(u32 offset, u32 val);
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u8 hdmirx_rd_cor(u32 addr, u8 port);
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void hdmirx_wr_cor(u32 addr, u8 data, u8 port);
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bool hdmirx_poll_cor(u32 addr, u8 exp_data, u8 mask, u32 max_try, u8 port);
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@@ -60,7 +60,8 @@ int vga_tuning_min = 0x21;
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int vga_tuning_max = 0x26;
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int cal_phy_time;
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enum frl_train_sts_e frl_train_sts = E_FRL_TRAIN_START;
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/* i2c monitor */
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#define I2C_BUFF_SIZE 0x1000
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/* for T3X 2.0 */
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static const u32 phy_misc_t3x_20[][2] = {
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/* 0x18 0x1c */
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@@ -4825,6 +4826,208 @@ bool is_frl_train_finished(void)
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return ret;
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}
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void rx_i2c_dbg_monitor(void)
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{
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u32 data32;
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if (rx_info.chip_id != CHIP_ID_T3X)
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return;
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data32 = rd_reg_clk_ctl(T3X_I2C_MONITOR_INTR_STATUS);
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if (data32 > 3) { //ignore start abnormal
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_START, 0x0);
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rx_i2c_dump();
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wr_reg_clk_ctl(T3X_I2C_MONITOR_INTR_STATUS, data32);
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}
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}
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static void rx_parse_i2c_data(u8 *buf, int size)
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{
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static const char * const ack_print[] = {"ACK", "NAK"};
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static const char * const wr_print[] = {"Write", "Read"};
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u8 type, data, ack, wr;
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int i;
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if (!buf || size < 4)
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return;
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for (i = 0; i < size; i += 4) {
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/*
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* |31..29|28.......9|8..1| 0|
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* |type |delta time|data|ack|
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*/
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if (!buf[i] && !buf[i + 1] && !buf[i + 2] && !buf[i + 3])
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break;
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type = (buf[i + 3] & MSK(3, 5)) >> 5;
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data = (buf[i] & MSK(7, 1)) >> 1 | (buf[i + 1] & 0x1) << 7;
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ack = buf[i] & 0x1;
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wr = data & 0x1;
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switch (type) {
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case E_DATA:
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rx_pr("0x%x + %s\n", data, ack_print[ack]);
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break;
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case E_START_DATA:
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rx_pr("%s to [0x%x] + %s\n", wr_print[wr], data, ack_print[ack]);
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break;
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case E_STOP_DATA:
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rx_pr("0x%x + %s + Stop\n", data, ack_print[ack]);
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break;
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case E_START_DATA_STOP:
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rx_pr("%s to [0x%x] + %s + Stop\n", wr_print[wr], data, ack_print[ack]);
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break;
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case E_STOP_ABNORMAL:
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rx_pr("!!STOP Abnormal(incomplete data)\n");
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break;
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case E_START_ABNORMAL:
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if (ack) {
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rx_pr("!!Start Abnormal: %s to [0x%x] + %s\n",
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wr_print[wr], data, ack_print[ack]);
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} else {
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rx_pr("!!Start Abnormal(incomplete data)\n");
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}
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break;
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case E_TIME_OUT:
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if (ack)
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rx_pr("!!time out(no data)\n");
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else
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rx_pr("!!time out + 0x%x\n", data);
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break;
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default:
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if ((data >> 5) == 0) {
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if (ack)
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rx_pr("HPD rise\n");
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else
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rx_pr("HPD fall\n");
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} else {
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rx_pr("!!other type:0x%x\n", data);
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}
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break;
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}
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}
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rx_pr("i:0x%x\n", i);
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}
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void rx_i2c_monitor(u8 sel, u8 smp_mod, u8 trig_mod, u8 dump_mod)
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{
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u8 *src = NULL;
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u32 data32;
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data32 = 0;
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data32 |= (smp_mod == 3 ? 1 : 0) << 31; //[31] bist_mode exist bug, can't use
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data32 |= (dump_mod & 0x1f) << 16; //[20-16]dump mode
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data32 |= 0x0 << 4; //[4] clk_free
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data32 |= (smp_mod & 0x3) << 2; //[3:2] smp_mode
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data32 |= 0x1 << 1; //[1] hpd_en
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data32 |= (trig_mod & 0x1) << 0; //[0] trig_mode
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_CNTL, data32);
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data32 = 0;
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data32 |= (sel >= 6 ? 1 << (sel - 6) : 0) << 24; //[31:24] sel input hpd to monitor
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data32 |= (1 << sel) << 0; //[23:0] sel input scl to monitor
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_SEL, data32);
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data32 = 0;
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data32 |= 0x2008 << 16; //[31:16] scl filter control
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data32 |= 0x2008 << 0; //[15: 0] sda filter control
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_FLT, data32);
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data32 = 0;
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data32 |= 0x7 << 0; //[15: 0] sda filter control
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_FLT_HPD, data32);
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data32 = 0;
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data32 |= 0xa << 16; //[31:16] time tick in smp_clk
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data32 |= 0x1 << 8; //[ 8] smp_clk enable
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data32 |= 0x5 << 0; //[ 7: 0] smp_clk div, cec sample:0x48
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_CLK, data32);
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data32 = 0;
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data32 |= 0x3ff << 0; //[10:0]
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wr_reg_clk_ctl(T3X_I2C_MONITOR_INTR_MASK, data32);
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rx_info.i2c_buff.pg_addr = alloc_pages(GFP_KERNEL, 0);
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src = (u8 *)kmap_atomic(rx_info.i2c_buff.pg_addr);
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memset(src, 0x0, I2C_BUFF_SIZE);
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kunmap_atomic(src);
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rx_info.i2c_buff.phy_addr = page_to_phys(rx_info.i2c_buff.pg_addr);
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if (rx_info.i2c_buff.phy_addr) {
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wr_reg_clk_ctl(T3X_I2C_MONITOR_DDR_START_ADDR,
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rx_info.i2c_buff.phy_addr >> 4);
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wr_reg_clk_ctl(T3X_I2C_MONITOR_DDR_END_ADDR,
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(rx_info.i2c_buff.phy_addr + I2C_BUFF_SIZE) >> 4);
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}
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data32 = 0;
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data32 |= 0x1 << 4; //[ 4] endian in 32 bit
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data32 |= 0x0 << 0; //[3:0] burst length
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wr_reg_clk_ctl(T3X_I2C_MONITOR_DDR_CNTL, data32);
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//smp start,config this bit after all the other reg has been ready
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wr_reg_clk_ctl(T3X_I2C_MONITOR_SMP_START, 0x1);
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}
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static void rx_i2c_reg_dump(void)
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{
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rx_pr("T3X_I2C_MONITOR_SMP_CNTL: 0x%x-0x%x\n", T3X_I2C_MONITOR_SMP_CNTL,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_SMP_CNTL));
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rx_pr("T3X_I2C_MONITOR_SMP_SEL: 0x%x-0x%x\n", T3X_I2C_MONITOR_SMP_SEL,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_SMP_SEL));
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rx_pr("T3X_I2C_MONITOR_SMP_FLT: 0x%x-0x%x\n", T3X_I2C_MONITOR_SMP_FLT,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_SMP_FLT));
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rx_pr("T3X_I2C_MONITOR_SMP_FLT_HPD: 0x%x-0x%x\n", T3X_I2C_MONITOR_SMP_FLT_HPD,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_SMP_FLT_HPD));
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rx_pr("T3X_I2C_MONITOR_SMP_CLK: 0x%x-0x%x\n", T3X_I2C_MONITOR_SMP_CLK,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_SMP_CLK));
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rx_pr("T3X_I2C_MONITOR_INTR_MASK: 0x%x-0x%x\n", T3X_I2C_MONITOR_INTR_MASK,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_INTR_MASK));
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rx_pr("T3X_I2C_MONITOR_DDR_START_ADDR: 0x%x-0x%x\n", T3X_I2C_MONITOR_DDR_START_ADDR,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_START_ADDR));
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rx_pr("T3X_I2C_MONITOR_DDR_END_ADDR: 0x%x-0x%x\n", T3X_I2C_MONITOR_DDR_END_ADDR,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_END_ADDR));
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rx_pr("T3X_I2C_MONITOR_DDR_CNTL: 0x%x-0x%x\n", T3X_I2C_MONITOR_DDR_CNTL,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_CNTL));
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}
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void rx_i2c_dump(void)
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{
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//int i, j;
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u8 *i2c_buff = NULL;
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u8 *src_buf = NULL;
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int buf_cnt;
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if (log_level & REG_LOG)
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rx_i2c_reg_dump();
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i2c_buff = kmalloc(I2C_BUFF_SIZE, GFP_KERNEL);
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if (!i2c_buff)
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return;
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memset(i2c_buff, 0, I2C_BUFF_SIZE);
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src_buf = (u8 *)kmap_atomic(rx_info.i2c_buff.pg_addr);
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if (!src_buf) {
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kfree(i2c_buff);
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return;
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}
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memcpy(i2c_buff, src_buf, I2C_BUFF_SIZE);
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/*
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*for (i = 0; i < 128; i++) {
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* for (j = 0; j < 32; j++)
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* pr_cont("%02X ", i2c_buff[i * 32 + j]);
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* rx_pr("\n");
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*}
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*/
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kunmap_atomic(src_buf);
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buf_cnt = (rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_WPTR) -
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rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_START_ADDR)) << 4;
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rx_pr("buf_cnt:wptr:0x%x-start:0x%x=0x%x\n",
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rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_WPTR) << 4,
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rd_reg_clk_ctl(T3X_I2C_MONITOR_DDR_START_ADDR) << 4,
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buf_cnt);
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rx_parse_i2c_data(i2c_buff, I2C_BUFF_SIZE);
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kfree(i2c_buff);
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}
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void rx_frl_train_handler(struct work_struct *work)
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{
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hdmi_tx_rx_frl_training_main(E_PORT2);
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@@ -134,6 +134,59 @@
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#define T3X_CLKCTRL_AUD21_PLL_CTRL3 (0x02ed << 2)
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#define T3X_CLKCTRL_AUD21_PLL_STS (0x02ee << 2)
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/* i2c monitor reg */
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#define T3X_I2C_MONITOR_BASE 0xfe014000
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#define T3X_I2C_MONITOR_SMP_START (0x14000 + (0x000 << 2))
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#define T3X_I2C_MONITOR_SMP_SEL (0x14000 + (0x001 << 2))
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#define T3X_I2C_MONITOR_SMP_CNTL (0x14000 + (0x002 << 2))
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#define T3X_I2C_MONITOR_SMP_FLT (0x14000 + (0x003 << 2))
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#define T3X_I2C_MONITOR_SMP_FLT_HPD (0x14000 + (0x004 << 2))
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#define T3X_I2C_MONITOR_SMP_I2C_TIMEOUT_TH (0x14000 + (0x005 << 2))
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#define T3X_I2C_MONITOR_SMP_CLK (0x14000 + (0x006 << 2))
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#define T3X_I2C_MONITOR_DDR_START_ADDR (0x14000 + (0x007 << 2))
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#define T3X_I2C_MONITOR_DDR_END_ADDR (0x14000 + (0x008 << 2))
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#define T3X_I2C_MONITOR_DDR_CNTL (0x14000 + (0x009 << 2))
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#define T3X_I2C_MONITOR_INTR_MASK (0x14000 + (0x00a << 2))
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#define T3X_I2C_MONITOR_DDR_WPTR (0x14000 + (0x00b << 2))
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#define T3X_I2C_MONITOR_DDR_BOUND_CNT (0x14000 + (0x00c << 2))
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#define T3X_I2C_MONITOR_AXI_CMD_PENDING (0x14000 + (0x00d << 2))
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#define T3X_I2C_MONITOR_SMP_STATUS (0x14000 + (0x00e << 2))
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#define T3X_I2C_MONITOR_SMP_I2C_BUSY_CNT (0x14000 + (0x00f << 2))
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#define T3X_I2C_MONITOR_AXI_STATUS (0x14000 + (0x010 << 2))
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#define T3X_I2C_MONITOR_INTR_STATUS (0x14000 + (0x011 << 2))
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#define T3X_I2C_MONITOR_AXI_CMD_CNT (0x14000 + (0x012 << 2))
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enum i2c_sample_mode_e {
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E_FUNC_SAMPLE,
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E_I2C_WAVE_SAMPLE,
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E_CEC_WAVE_SAMPLE,
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E_BIST_MODE
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};
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enum i2c_trigger_mode_e {
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E_HW_TRIGGER,
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E_SW_TRIGGER
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};
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enum i2c_dump_mode_e {
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E_ABNORMAL_START0 = 0x1,
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E_ABNORMAL_START1 = 0x2,
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E_ABNORMAL_STOP = 0x4,
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E_I2C_TIMEOUT = 0x8,
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E_HPD_CHANGE = 0x10,
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E_DUMP_ALL = 0x1f
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};
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enum i2c_data_type_e {
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E_DATA,
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E_START_DATA,
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E_STOP_DATA,
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E_START_DATA_STOP,
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E_STOP_ABNORMAL,
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E_START_ABNORMAL,
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E_TIME_OUT
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};
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enum frl_train_sts_e {
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E_FRL_TRAIN_START,
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E_FRL_TRAIN_FINISH,
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@@ -230,6 +283,9 @@ bool is_fsm_ready_t3x(void);
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bool rx_get_clkready_sts(u8 port);
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bool rx_get_valid_m_sts(u8 port);
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void rx_i2c_dbg_monitor(void);
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void rx_i2c_monitor(u8 sel, u8 smp_mod, u8 trig_mod, u8 dump_mod);
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void rx_i2c_dump(void);
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//void reset_pcs(void);
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/*function declare end*/
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@@ -8413,6 +8413,12 @@ int hdmirx_debug(const char *buf, int size)
|
||||
rx_pr("phy_addr = 0x%x, size = 0x%x, maped:%px\n",
|
||||
rx_reg_maps[i].phy_addr, size, rx_reg_maps[i].p);
|
||||
}
|
||||
} else if (strncmp(tmpbuf, "i2c_monitor", 10) == 0) {
|
||||
rx_i2c_monitor(6 + port, E_FUNC_SAMPLE, E_SW_TRIGGER, E_DUMP_ALL);
|
||||
rx_pr("i2c_monitor start\n");
|
||||
} else if (strncmp(tmpbuf, "i2c_dump", 7) == 0) {
|
||||
rx_pr("i2c_dump\n");
|
||||
rx_i2c_dump();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -8699,6 +8705,7 @@ void hdmirx_timer_handler(struct timer_list *t)
|
||||
rx_clkmsr_monitor();
|
||||
rx_hpd_monitor();
|
||||
rx_edid_monitor();
|
||||
rx_i2c_dbg_monitor();
|
||||
if (rx_info.chip_id == CHIP_ID_T3X)
|
||||
hdmirx_timer_t3x();
|
||||
else
|
||||
|
||||
Reference in New Issue
Block a user