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uart: bringup c1 uart [1/1]

Browse Source 
PD#SWPL-121178

Problem:
need bringup c1 uart

Solution:
add c1 uart config

Verify:
c1_ae400

Change-Id: I73594f0ab58491ea447b77dc39e03497681c7af7
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
This commit is contained in:
Yu Tu
2023-05-15 17:23:31 +08:00
committed by pengzhao.liu
parent 2d15695777
commit c8506fefff
4 changed files with 16 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-c1-c308x-ae400-nand.dts
+1 -1
View File
@@ -1292,7 +1292,7 @@
};
&uart_C {
status = "okay";
status = "disabled";
};
&i2c3 {
arch/arm64/boot/dts/amlogic/meson-c1-c308x-ae400.dts
+1 -1
View File
@@ -1237,7 +1237,7 @@
};
&uart_C {
status = "okay";
status = "disabled";
rs485 = <0>;
rts-gpio = <&gpio GPIOA_0 GPIO_ACTIVE_HIGH>;
};
arch/arm64/boot/dts/amlogic/meson-c1-c308x-ae401.dts
+1 -1
View File
@@ -1317,7 +1317,7 @@
};
&uart_C {
status = "okay";
status = "disabled";
rs485 = <1>;
rts-gpio = <&gpio GPIOA_0 GPIO_ACTIVE_HIGH>;
};
arch/arm64/boot/dts/amlogic/meson-c1.dtsi
+13 -8
View File
@@ -397,8 +397,8 @@
reg = <0x0 0x1c00 0x0 0x18>;
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
//clocks = <&xtal
// &clkc CLKID_UART_A>;
clocks = <&xtal
&clkc CLKID_SYS_UART_A>;
clock-names = "clk_uart",
"clk_gate";
xtal_tick_en = <1>;
@@ -417,8 +417,7 @@
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
//pinctrl-names = "default";
//pinctrl-0 = <&b_uart_enable_pins1>;
xtal_tick_en = <1>;
};
uart_C: serial@7000 {
@@ -440,8 +439,8 @@
reg = < 0x0 0x9c00 0x0 0x18>;
interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
//clocks = <&xtal
// &clkc CLKID_SYS_UART_D>;
clocks = <&xtal
&clkc CLKID_SYS_UART_D>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
@@ -454,8 +453,8 @@
reg = < 0x0 0xa000 0x0 0x18>;
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
//clocks = <&xtal
// &clkc CLKID_SYS_UART_E>;
clocks = <&xtal
&clkc CLKID_SYS_UART_E>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
@@ -1823,6 +1822,8 @@
"uart_a_cts",
"uart_a_rts";
function = "uart_a";
bias-pull-up;
drive-strength = <3>;
};
};
@@ -1831,6 +1832,8 @@
groups = "uart_a_tx_x14",
"uart_a_rx_x15";
function = "uart_a";
bias-pull-up;
drive-strength = <3>;
};
};
@@ -1867,6 +1870,8 @@
"uart_c_cts",
"uart_c_rts";
function = "uart_c";
bias-pull-up;
drive-strength = <3>;
};
};