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vpp: sync scale down improve change for t6d [1/1]

Browse Source 
PD#SWPL-180371

Problem:
s6/s7d safa scaler down improve sync to t6d

Solution:
s6/s7d safa scaler down improve sync to t6d

Verify:
t6d

Change-Id: Ib839cfef8d8f64a75339aed3bf37473d3c6a7e2f
Signed-off-by: hai.cao <hai.cao@amlogic.com>
This commit is contained in:
hai.cao
2024-08-06 15:11:32 +08:00
committed by jian.hu
parent b828a5ef30
commit cb84d8ab29
6 changed files with 100 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/video_sink/video.c
+1
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@@ -15323,6 +15323,7 @@ static struct video_device_hw_s t6d_dev_property = {
.sr01_num = 0,
.vd1_vsr_safa_support = 1,
.frm2fld_support = 0,
.vsr_nonlinear_support = 1,
};
#endif
drivers/media/video_sink/video_hw.c
+1
View File
@@ -14717,6 +14717,7 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo)
cur_dev->frm2fld_support =
p_amvideo->dev_property.frm2fld_support;
cur_dev->dejaggy_support = p_amvideo->dev_property.dejaggy_support;
cur_dev->vsr_nonlinear_support = p_amvideo->dev_property.vsr_nonlinear_support;
if (cur_dev->aisr_support)
cur_dev->pps_auto_calc = 1;
if (cur_dev->display_module == T7_DISPLAY_MODULE) {
drivers/media/video_sink/video_priv.h
+2
View File
@@ -310,6 +310,7 @@ struct video_dev_s {
u8 frm2fld_support;
u8 display_device_cnt;
u8 dejaggy_support;
u8 vsr_nonlinear_support;
};
struct video_layer_s;
@@ -771,6 +772,7 @@ struct video_device_hw_s {
u8 vd1_vsr_safa_support;
u8 frm2fld_support;
u8 dejaggy_support;
u8 vsr_nonlinear_support;
};
struct amvideo_device_data_s {
drivers/media/video_sink/video_reg.c
+2 -1
View File
@@ -1056,13 +1056,13 @@ struct hw_vsr_safa_reg_s s6_vsr_safa_reg = {
SAFA_PPS_VSC_START_PHASE_STEP,
SAFA_PPS_VSC_INIT,
SAFA_PPS_HSC_INIT,
S6_SAFA_PPS_BOT_VSC_INIT,
SAFA_PPS_SC_MISC,
S6_SAFA_PPS_CNTL_SCALE_COEF_IDX_LUMA,
S6_SAFA_PPS_CNTL_SCALE_COEF_LUMA,
S6_SAFA_PPS_CNTL_SCALE_COEF_IDX_CHRO,
S6_SAFA_PPS_CNTL_SCALE_COEF_CHRO,
SAFA_PPS_DEJAGGY_CTRL,
S6_SAFA_PPS_BOT_VSC_INIT,
};
struct hw_vsr_safa_reg_s vsr_safa_reg_t6d = {
@@ -1105,6 +1105,7 @@ struct hw_vsr_safa_reg_s vsr_safa_reg_t6d = {
T6D_SAFA_PPS_CNTL_SCALE_COEF_LUMA,
T6D_SAFA_PPS_CNTL_SCALE_COEF_IDX_CHRO,
T6D_SAFA_PPS_CNTL_SCALE_COEF_CHRO,
T6D_SAFA_PPS_DEJAGGY_CTRL,
};
struct hw_vsr_safa_nonlinear_reg_s vsr_safa_nonlinear_reg = {
drivers/media/video_sink/video_safa.c
+82 -36
View File
@@ -283,6 +283,8 @@ void dump_vd_vsr_safa_nonlinear_reg(void)
u32 reg_addr, reg_val = 0;
struct hw_vsr_safa_nonlinear_reg_s *vsr_non_linear_reg;
if (!cur_dev->vsr_nonlinear_support)
return;
vsr_non_linear_reg = &vsr_safa_nonlinear_reg;
pr_info("vsr safa nonlinear regs:\n");
@@ -516,6 +518,11 @@ static void safa_pps_scale_set_coef(struct vsr_setting_s *vsr,
((pps_lut_tap6_s11_default[i][4] & 0xff) << 16) |
(((pps_lut_tap6_s11_default[i][5] >> 8) & 0xff) << 8) |
((pps_lut_tap6_s11_default[i][5] & 0xff) << 0));
rdma_wr(SAFA_PPS_CNTL_SCALE_COEF,
(((pps_lut_tap6_s11_default[i][4] >> 8) & 0xff) << 24) |
((pps_lut_tap6_s11_default[i][4] & 0xff) << 16) |
(((pps_lut_tap6_s11_default[i][5] >> 8) & 0xff) << 8) |
((pps_lut_tap6_s11_default[i][5] & 0xff) << 0));
}
/* ver 4tap */
@@ -725,13 +732,18 @@ static void set_cfg_pi_safa(struct vsr_setting_s *vsr)
/* when safa size <= 2048 and scaler up, dejaggy_enable */
if (cur_dev->dejaggy_support &&
hsize_in <= 2048 &&
(hsize_out > hsize_in || vsize_out > vsize_in) &&
!vsr_safa->prev_en &&
vsr_top->is_interlaced)
vsr_safa->dejaggy_en = true;
else
vsr_top->is_interlaced) {
if (video_is_meson_s6_cpu() && hsize_in <= 2048)
vsr_safa->dejaggy_en = true;
else if (video_is_meson_t6d_cpu() &&
(hsize_in <= 1024 ||
(vsr_top->input_422_en && hsize_in <= 2048)))
vsr_safa->dejaggy_en = true;
} else {
vsr_safa->dejaggy_en = false;
}
if (hsize_out <= 45)
vsr_top->sharpness_en = false;
@@ -1108,7 +1120,8 @@ void set_safa_pps(struct vsr_setting_s *vsr)
u32 filt_num_c = 0, step = 0;
vsr_reg = &vd_layer[0].vsr_safa_reg;
vsr_nonlinear_reg = &vsr_safa_nonlinear_reg;
if (cur_dev->vsr_nonlinear_support)
vsr_nonlinear_reg = &vsr_safa_nonlinear_reg;
adp_tap_alp_mode = 1;
beta_mode = 1;
sr_delta_alp_mode = 1;
@@ -1182,36 +1195,55 @@ void set_safa_pps(struct vsr_setting_s *vsr)
safa_pps_scale_set_coef(vsr,
vsr_reg->safa_pps_cntl_scale_coef_idx_chro,
vsr_reg->safa_pps_cntl_scale_coef_chro);
if (pre_scaler[0].pre_hscaler_ntap == PRE_HSCALER_2TAP ||
pre_scaler[0].pre_vscaler_ntap == PRE_VSCALER_2TAP)
filt_num_c = 2;
else
filt_num_c = 4;
//reg config
rdma_wr_bits(vsr_reg->safa_pps_sr_422_en,
input_422_en, 0, 1);
if (input_422_en)
filt_num_c = 2;
else
filt_num_c = 4;
rdma_wr(vsr_reg->safa_pps_pre_scale,
(4 << 16) |
(filt_num_c << 12) |
(4 << 8) |
(preh_ratio << 4) |
(prev_ratio << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_y1,
(0 << 16) |
(0 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_y0,
(64 << 16) |
(192 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_c1,
(0 << 16) |
(0 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_c0,
(0 << 16) |
(256 << 0));
rdma_wr(vsr_reg->safa_pps_pre_vscale_coef,
(64 << 16) |
(194 << 0));
if (pre_scaler[0].pre_hscaler_ntap == PRE_HSCALER_2TAP ||
pre_scaler[0].pre_vscaler_ntap == PRE_VSCALER_2TAP) {
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_y1,
(0 << 16) |
(0 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_y0,
(0 << 16) |
(256 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_c1,
(0 << 16) |
(0 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_c0,
(0 << 16) |
(256 << 0));
rdma_wr(vsr_reg->safa_pps_pre_vscale_coef,
(0 << 16) |
(256 << 0));
} else {
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_y1,
(0 << 16) |
(0 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_y0,
(64 << 16) |
(192 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_c1,
(0 << 16) |
(0 << 0));
rdma_wr(vsr_reg->safa_pps_pre_hscale_coef_c0,
(64 << 16) |
(194 << 0));
rdma_wr(vsr_reg->safa_pps_pre_vscale_coef,
(64 << 16) |
(194 << 0));
}
rdma_wr_bits(vsr_reg->safa_pps_hw_ctrl,
postsc_size_mux, 1, 1);
rdma_wr_bits(vsr_reg->safa_pps_hw_ctrl,
@@ -1220,12 +1252,17 @@ void set_safa_pps(struct vsr_setting_s *vsr)
adp_tap_alp_mode, 8, 2);
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
beta_mode, 12, 2);
/* changed since t6d, s7d bit24, t6d bit25 */
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
drt_intp_en, 25, 1);
/* new add for t6d */
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
drt_intp_chrm_en, 24, 1);
if (video_is_meson_t6d_cpu()) {
/* changed since t6d, s7d bit24, t6d bit25 */
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
drt_intp_en, 25, 1);
/* new add for t6d */
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
drt_intp_chrm_en, 24, 1);
} else {
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
drt_intp_en, 24, 1);
}
rdma_wr_bits(vsr_reg->safa_pps_yuv_sharpen_en,
sharp_en, 4, 1);
rdma_wr_bits(vsr_reg->safa_pps_dir_en_mode,
@@ -1249,21 +1286,27 @@ void set_safa_pps(struct vsr_setting_s *vsr)
rdma_wr_bits(vsr_reg->safa_pps_hsc_init,
vsr_top->pi_safa_hsc_ini_phase, 0, 16);
rdma_wr_bits(vsr_reg->safa_pps_vsc_init,
vsr_top->pi_safa_vsc_ini_integer, 0, 5);
vsr_top->pi_safa_vsc_ini_integer, 16, 5);
rdma_wr_bits(vsr_reg->safa_pps_hsc_init,
vsr_top->pi_safa_hsc_ini_integer, 0, 5);
rdma_wr_bits(vsr_reg->safa_pps_bot_vsc_init,
vsr_top->pi_safa_vsc_ini_phase, 0, 16);
vsr_top->pi_safa_hsc_ini_integer, 16, 5);
if (!video_is_meson_s7d_cpu())
rdma_wr_bits(vsr_reg->safa_pps_bot_vsc_init,
vsr_top->pi_safa_vsc_ini_phase, 0, 16);
rdma_wr_bits(vsr_reg->safa_pps_sc_misc,
prev_en, 4, 1);
rdma_wr_bits(vsr_reg->safa_pps_sc_misc,
preh_en, 8, 1);
rdma_wr_bits(vsr_reg->safa_pps_hw_ctrl,
postsc_en, 2, 1);
//scale down disable analy_en
if (vsr->vsr_top.hsize_in >= vsr->vsr_top.hsize_out ||
vsr->vsr_top.vsize_in >= vsr->vsr_top.vsize_out)
analy_en = 0;
rdma_wr_bits(vsr_reg->safa_pps_hw_ctrl,
analy_en, 4, 1);
if (vsr_safa->nonlinear_4region_en) {
if (cur_dev->vsr_nonlinear_support &&
vsr_safa->nonlinear_4region_en) {
//Wr_reg_bits(SAFA_PPS_INTERP_EN_MODE,1,26,1);
//Wr_reg_bits(SAFA_PPS_HW_CTRL,1,19,1);
rdma_wr_bits(vsr_reg->safa_pps_interp_en_mode,
@@ -1296,6 +1339,9 @@ void set_safa_pps(struct vsr_setting_s *vsr)
}
rdma_wr_bits(vsr_reg->safa_pps_hw_ctrl,
safa_pps_top_en, 8, 1);
if (cur_dev->dejaggy_support)
rdma_wr_bits(vsr_reg->safa_pps_dejaggy_ctrl,
vsr_safa->dejaggy_en, 31, 1);
}
static void set_vsr_input_format(struct vsr_setting_s *vsr)
drivers/media/video_sink/video_safa_reg.h
+12
View File
@@ -526,6 +526,18 @@
//Bit 2 reg_postsc_en // unsigned , RW, default = 0 ,reg_postsc_en
//Bit 1 reg_size_mux // unsigned , RW, default = 0 ,hsize sel
//Bit 0 reg_prevsc_outside_en // unsigned , RW, default = 1 ,video1 scale out enable
#define T6D_SAFA_PPS_DEJAGGY_CTRL 0x5191
//Bit 31 reg_dejaggy_en // unsigned , RW, default = 0
//Bit 30 reg_dejaggy_dps_en_0 // unsigned , RW, default = 0
//Bit 29 reg_dejaggy_dps_en_1 // unsigned , RW, default = 0
//Bit 28 reg_dejaggy_sameside_mode // unsigned , RW, default = 0
//Bit 27:25 reserved
//Bit 24 reg_dejaggy_sameside_prtct // unsigned , RW, default = 0
//Bit 23:16 reserved
//Bit 15:12 reg_dejaggy_procluma_alpha_1 // unsigned , RW, default = 15
//Bit 11: 8 reg_dejaggy_procluma_alpha_0 // unsigned , RW, default = 15
//Bit 7: 4 reg_dejaggy_procchrm_alpha_1 // unsigned , RW, default = 15
//Bit 3: 0 reg_dejaggy_procchrm_alpha_0 // unsigned , RW, default = 15
#define T6D_SAFA_PPS_CNTL_SCALE_COEF_IDX_LUMA 0x5192
//Bit 31:15 reserved
//Bit 14 reg_index_inc_luma // unsigned , RW, default = 0 ,index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)