usb: fix kernel5.15 typo err [1/1]

PD#SWPL-103669

Problem:
typo check report errors

Solution:
fix according to the prompt

Verify:
AR321

Change-Id: I5ab217c1f665afa5c7334df344ac70671c2a980b
Signed-off-by: dian.shao <dian.shao@amlogic.com>

drivers/usb/dwc_otg/310/common_port/dwc_cc.h

@@ -93,7 +93,7 @@ extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
  * @param cdid A pointer to the 16-byte CDID.  This value will be copied.
  * @param name An optional host friendly name as defined in the association model
  * spec.  Must be a UTF16-LE unicode string.  Can be NULL to indicated no name.
- * @param length The length othe unicode string.
+ * @param length The length of the unicode string.
  * @return A unique identifier used to refer to this context that is valid for
  * as long as this context is still in the list. */
 extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,

drivers/usb/dwc_otg/310/common_port/dwc_os.h

@@ -789,7 +789,7 @@ extern char *DWC_STRDUP(char const *str);
  * "0x" prefix if base 16.  The remaining characters must be valid digits for
  * the number and end with a NULL character.  If any invalid characters are
  * encountered or it returns with a negative error code and the results of the
- * conversion are undefined.  On sucess it returns 0.  Overflow conditions are
+ * conversion are undefined.  On success it returns 0.  Overflow conditions are
  * undefined.  An example implementation using atoi() can be referenced from the
  * Linux implementation. */
 extern int DWC_ATOI(const char *str, int32_t *value);
@@ -1026,7 +1026,7 @@ struct dwc_spinlock;
 /** Type for a spinlock */
 typedef struct dwc_spinlock dwc_spinlock_t;
 
-/** Type for the 'flags' argument to spinlock funtions */
+/** Type for the 'flags' argument to spinlock functions */
 typedef unsigned long dwc_irqflags_t;
 
 /** Returns an initialized lock variable.  This function should allocate and
@@ -1206,7 +1206,7 @@ extern uint32_t DWC_TIME(void);
  * - Crypto - Used internally only.  See dwc_crypto.h
  *
  *
- * @section prereq Prerequistes For dwc_os.h
+ * @section prereq Prerequisites For dwc_os.h
  * @subsection types Data Types
  *
  * The dwc_os.h file assumes that several low-level data types are pre defined for the

drivers/usb/dwc_otg/310/dwc_otg_adp.c

@@ -186,7 +186,7 @@ static void adp_vbuson_timeout(void *ptr)
  * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
  * not asserted within 1.1 seconds.
  *
- * @param core_if the pointer to core_if strucure.
+ * @param core_if the pointer to core_if structure.
  */
 void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t *core_if)
 {
@@ -349,7 +349,7 @@ uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t *core_if)
  * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
  * within 3 seconds.
  *
- * @param core_if the pointer to core_if strucure.
+ * @param core_if the pointer to core_if structure.
  */
 void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t *core_if)
 {
@@ -360,7 +360,7 @@ void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t *core_if)
 /**
  * Starts the ADP Sense
  *
- * @param core_if the pointer to core_if strucure.
+ * @param core_if the pointer to core_if structure.
  */
 uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t *core_if)
 {
@@ -395,7 +395,7 @@ uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t *core_if)
 /**
  * Stops the ADP Probing
  *
- * @param core_if the pointer to core_if strucure.
+ * @param core_if the pointer to core_if structure.
  */
 uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t *core_if)
 {
@@ -418,7 +418,7 @@ uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t *core_if)
 /**
  * Stops the ADP Sensing
  *
- * @param core_if the pointer to core_if strucure.
+ * @param core_if the pointer to core_if structure.
  */
 uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t *core_if)
 {
@@ -517,7 +517,7 @@ void dwc_otg_adp_init(dwc_otg_core_if_t *core_if)
 	core_if->adp.vbuson_timer_started = 0;
 	core_if->adp.probe_counter = 0;
 	core_if->adp.gpwrdn = 0;
-	core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
+	core_if->adp.attached = DWC_OTG_ADP_UNKNOWN;
 	/* Initialize timers */
 	core_if->adp.sense_timer =
 	    DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);

drivers/usb/dwc_otg/310/dwc_otg_adp.h

@@ -44,7 +44,7 @@
 
 #define DWC_OTG_ADP_UNATTACHED	0
 #define DWC_OTG_ADP_ATTACHED	1
-#define DWC_OTG_ADP_UNKOWN	2
+#define DWC_OTG_ADP_UNKNOWN	2
 
 typedef struct dwc_otg_adp {
 	uint32_t adp_started;

drivers/usb/dwc_otg/310/dwc_otg_cfi.c

@@ -1722,7 +1722,7 @@ static int cfi_ep_get_concat_val(uint8_t *buf, struct dwc_otg_pcd *pcd,
 	buf += BS_CONCAT_VAL_HDR_LEN;
 
 	desc_count = ep->bm_concat->hdr.bDescCount;
-	/* Copy alll the wTxBytes to the buffer */
+	/* Copy all the wTxBytes to the buffer */
 	dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
 
 	retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;

drivers/usb/dwc_otg/310/dwc_otg_cil.c

@@ -253,7 +253,7 @@ dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr, int host_only
 		    core_if->hwcfg3.b.xfer_size_cntr_width);
 
 	/*
-	 * Set the SRP sucess bit for FS-I2c
+	 * Set the SRP success bit for FS-I2c
 	 */
 	core_if->srp_success = 0;
 	core_if->srp_timer_started = 0;
@@ -384,7 +384,7 @@ void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
 }
 
 /**
- * This function initializes the commmon interrupts, used in both
+ * This function initializes the common interrupts, used in both
  * device and host modes.
  *
  * @param core_if Programming view of the DWC_otg controller
@@ -1521,7 +1521,7 @@ void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
 	/* Enable common interrupts */
 	dwc_otg_enable_common_interrupts(core_if);
 
-	/* Do device or host intialization based on mode during PCD
+	/* Do device or host initialization based on mode during PCD
 	 * and HCD initialization  */
 	if (dwc_otg_is_host_mode(core_if)) {
 		DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
@@ -1861,7 +1861,7 @@ void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
 
 	/* Clear all pending Device Interrupts */
 	/** @todo - if the condition needed to be checked
-	 *  or in any case all pending interrutps should be cleared?
+	 *  or in any case all pending interrupts should be cleared?
      */
 	if (core_if->multiproc_int_enable) {
 		for (i = 0; i < core_if->dev_if->num_in_eps; ++i)
@@ -2007,7 +2007,7 @@ void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
 		/*
 		 *	In 2.94a, pull_up is disabled after reset/power on.
 		 *    Gadget must call pull_up() to enable the connection.
-		 *    Here is the workarond code for BC detection changes
+		 *    Here is the workaround code for BC detection changes
 		 */
 		usb_peri_reg_t *peri;
 		usb_adp_bc_data_t adp_bc;
@@ -3840,7 +3840,7 @@ void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 			if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
 				/**
 				 * Enable the Non-Periodic Tx FIFO empty interrupt,
-				 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
+				 * or the Tx FIFO empty interrupt in dedicated Tx FIFO mode,
 				 * the data will be written into the fifo by the ISR.
 				 */
 				if (core_if->en_multiple_tx_fifo == 0) {
@@ -4069,7 +4069,7 @@ void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 			DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
 			/**
 			 * Enable the Non-Periodic Tx FIFO empty interrupt,
-			 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
+			 * or the Tx FIFO empty interrupt in dedicated Tx FIFO mode,
 			 * the data will be written into the fifo by the ISR.
 			 */
 			if (core_if->en_multiple_tx_fifo == 0) {
@@ -4591,7 +4591,7 @@ void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep,
 #endif
 
 	/**@todo NGS Where are the Periodic Tx FIFO addresses
-	 * intialized?	What should this be? */
+	 * initialized? What should this be? */
 
 	fifo = core_if->data_fifo[ep->num];
 
@@ -7296,7 +7296,7 @@ uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t *core_if)
  * Start the SRP timer to detect when the SRP does not complete within
  * 6 seconds.
  *
- * @param core_if the pointer to core_if strucure.
+ * @param core_if the pointer to core_if structure.
  */
 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t *core_if)
 {
@@ -7317,7 +7317,7 @@ void dwc_otg_initiate_srp(void *p)
 		return;
 	}
 
-	DWC_INFO("Session Request Initated\n");
+	DWC_INFO("Session Request Initiated\n");
 	mem.d32 = DWC_READ_REG32(addr);
 	mem.b.sesreq = 1;
 	DWC_WRITE_REG32(addr, mem.d32);

drivers/usb/dwc_otg/310/dwc_otg_cil.h

@@ -905,7 +905,7 @@ struct dwc_otg_core_if {
 	hcfg_data_t hcfg;
 	dcfg_data_t dcfg;
 
-	/** The operational State, during transations
+	/** The operational State, during transactions
 	 * (a_host>>a_peripherial and b_device=>b_host) this may not
 	 * match the core but allows the software to determine
 	 * transitions.
@@ -946,7 +946,7 @@ struct dwc_otg_core_if {
 	int vbus_power_pin_work_mask;
 	struct gpio_desc *usb_gpio_desc;
 
-	int swicth_int_reg;
+	int switch_int_reg;
 
 	/* Charger Detect Call back*/
 	int charger_detect;
@@ -1047,7 +1047,7 @@ struct dwc_otg_core_if {
 	 * active, 0xff otherwise */
 	uint8_t nextep_seq[MAX_EPS_CHANNELS];
 
-	/** Index of fisrt EP in nextep_seq array which should be re-enabled **/
+	/** Index of first EP in nextep_seq array which should be re-enabled **/
 	uint8_t first_in_nextep_seq;
 
 	/** Frame number while entering to ISR - needed for ISOCs **/

drivers/usb/dwc_otg/310/dwc_otg_core_if.h

@@ -595,7 +595,7 @@ extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t *core_if);
 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t *core_if, uint32_t val);
 
 /**
- * Get value of prtsusp field from the HPRT0 regsiter
+ * Get value of prtsusp field from the HPRT0 register
  */
 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t *core_if);
 /**
@@ -604,20 +604,20 @@ extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t *core_if);
 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t *core_if, uint32_t val);
 
 /**
- * Get value of ModeChTimEn field from the HCFG regsiter
+ * Get value of ModeChTimEn field from the HCFG register
  */
 extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t *core_if);
 /**
- * Set value of ModeChTimEn field from the HCFG regsiter
+ * Set value of ModeChTimEn field from the HCFG register
  */
 extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t *core_if, uint32_t val);
 
 /**
- * Get value of Fram Interval field from the HFIR regsiter
+ * Get value of Fram Interval field from the HFIR register
  */
 extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t *core_if);
 /**
- * Set value of Frame Interval field from the HFIR regsiter
+ * Set value of Frame Interval field from the HFIR register
  */
 extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t *core_if, uint32_t val);
 

drivers/usb/dwc_otg/310/dwc_otg_driver.c

@@ -1361,7 +1361,7 @@ static int dwc_otg_driver_probe(struct platform_device *pdev)
 	dwc_otg_device->core_if->charger_detect = charger_detect;
 	dwc_otg_device->core_if->non_normal_usb_charger_detect_delay = non_normal_usb_charger_detect_delay;
 	if (host_only_core && pmu_apply_power)
-		dwc_otg_device->core_if->swicth_int_reg = 1;
+		dwc_otg_device->core_if->switch_int_reg = 1;
 
 	if (port_type == USB_PORT_TYPE_HOST) {
 		/*

drivers/usb/dwc_otg/310/dwc_otg_hcd.c

@@ -498,7 +498,7 @@ static void dwc_otg_hcd_power_save(dwc_otg_hcd_t *hcd, int power_on)
 	DWC_WRITE_REG32(hcd->core_if->pcgcctl, pcgcctl.d32);
 	if (!hcd->auto_pm_suspend_flag) {
 		DWC_WRITE_REG32(&hcd->core_if->usb_peri_reg->dbg_uart, uart.d32);
-		if (hcd->core_if->swicth_int_reg) {
+		if (hcd->core_if->switch_int_reg) {
 			if (power_on) {
 				dwc_otg_enable_host_interrupts(hcd->core_if);
 				dwc_otg_enable_global_interrupts(hcd->core_if);
@@ -2240,7 +2240,7 @@ int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
 			break;
 		case UHF_PORT_INDICATOR:
 			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
-			/* Port inidicator not supported */
+			/* Port indicator not supported */
 			break;
 		case UHF_C_PORT_CONNECTION:
 			/* Clears drivers internal connect status change
@@ -2440,7 +2440,7 @@ int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
 					dwc_mdelay(1);
 				} while (--timeout);
 				if (!timeout)
-					DWC_WARN("Suspend wasn't genereted\n");
+					DWC_WARN("Suspend wasn't generated\n");
 
 				dwc_udelay(10);
 

drivers/usb/dwc_otg/310/dwc_otg_hcd.h

@@ -49,7 +49,7 @@
  * @file
  *
  * This file contains the structures, constants, and interfaces for
- * the Host Contoller Driver (HCD).
+ * the Host Controller Driver (HCD).
  *
  * The Host Controller Driver (HCD) is responsible for translating requests
  * from the USB Driver into the appropriate actions on the DWC_otg controller.

drivers/usb/dwc_otg/310/dwc_otg_hcd_linux.c

@@ -271,7 +271,7 @@ static int _complete(dwc_otg_hcd_t *hcd, void *urb_handle,
 		break;
 	default:
 		if (status)
-			DWC_PRINTF("Uknown urb status %d\n", status);
+			DWC_PRINTF("Unknown urb status %d\n", status);
 	}
 
 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
@@ -688,7 +688,7 @@ static int urb_enqueue(struct usb_hcd *hcd,
 						   !(usb_pipein(urb->pipe))));
 
 	buf = urb->transfer_buffer;
-	/*phys_to_virt api can not geting virt address,we can not use it.*/
+	/*phys_to_virt api can not get virt address,we can not use it.*/
 #if 0
 	if (hcd->self.uses_dma)
 		/*

drivers/usb/dwc_otg/310/dwc_otg_hcd_queue.c

@@ -320,12 +320,12 @@ dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd,
 /**
  * Checks that a channel is available for a periodic transfer.
  *
- * @return 0 if successful, negative error code otherise.
+ * @return 0 if successful, negative error code otherwise.
  */
 static int periodic_channel_available(dwc_otg_hcd_t *hcd)
 {
 	/*
-	 * Currently assuming that there is a dedicated host channnel for each
+	 * Currently assuming that there is a dedicated host channel for each
 	 * periodic transaction plus at least one host channel for
 	 * non-periodic transactions.
 	 */

drivers/usb/dwc_otg/310/dwc_otg_pcd.c

@@ -202,7 +202,7 @@ void dwc_otg_request_done(dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req,
 }
 
 /**
- * This function terminates all the requsts in the EP request queue.
+ * This function terminates all the requests in the EP request queue.
  */
 void dwc_otg_request_nuke(dwc_otg_pcd_ep_t *ep)
 {

drivers/usb/dwc_otg/310/dwc_otg_pcd.h

@@ -47,7 +47,7 @@ struct cfiobject;
  * @file
  *
  * This file contains the structures, constants, and interfaces for
- * the Perpherial Contoller Driver (PCD).
+ * the Peripheral Controller Driver (PCD).
  *
  * The Peripheral Controller Driver (PCD) for Linux will implement the
  * Gadget API, so that the existing Gadget drivers can be used. For

drivers/usb/dwc_otg/310/dwc_otg_pcd_if.h

@@ -239,7 +239,7 @@ extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t *pcd);
 
 /**
  * Start isochronous transfers on the endpoint referenced by ep_handle.
- * For isochronous transfers duble buffering is used.
+ * For isochronous transfers double buffering is used.
  * After processing each of buffers complete callback will be called with
  * status for each transaction.
  *
@@ -322,10 +322,10 @@ extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t *pcd);
 /** This function returns 1 if LPM Errata support is enabled, and 0 otherwise. */
 extern int dwc_otg_pcd_is_besl_enabled(dwc_otg_pcd_t *pcd);
 
-/** This function returns baseline_besl module parametr. */
+/** This function returns baseline_besl module parameter. */
 extern int dwc_otg_pcd_get_param_baseline_besl(dwc_otg_pcd_t *pcd);
 
-/** This function returns deep_besl module parametr. */
+/** This function returns deep_besl module parameter. */
 extern int dwc_otg_pcd_get_param_deep_besl(dwc_otg_pcd_t *pcd);
 
 /** This function returns 1 if remote wakeup is allowed and 0, otherwise. */

drivers/usb/dwc_otg/310/dwc_otg_pcd_intr.c

@@ -544,7 +544,7 @@ int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t *pcd)
 /**
  * This function is called when dedicated Tx FIFO Empty interrupt occurs.
  * The active request is checked for the next packet to be loaded into
- * apropriate Tx FIFO.
+ * appropriate Tx FIFO.
  */
 static int32_t write_empty_tx_fifo(dwc_otg_pcd_t *pcd, uint32_t epnum)
 {
@@ -1323,7 +1323,7 @@ int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t *pcd)
 }
 
 /**
- * This funcion stalls EP0.
+ * This function stalls EP0.
  */
 static inline void ep0_do_stall(dwc_otg_pcd_t *pcd, const int err_val)
 {
@@ -1474,7 +1474,7 @@ static inline void pcd_clear_halt(dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
 		 * epmismatch not yet implemented. */
 
 		/*
-		 * Above fixme is solved by implmenting a tasklet to call the
+		 * Above fixme is solved by implementing a tasklet to call the
 		 * start_next_request(), outside of interrupt context at some
 		 * time after the current time, after a clear-halt setup packet.
 		 * Still need to implement ep mismatch in the future if a gadget
@@ -2343,10 +2343,10 @@ static void complete_ep(dwc_otg_pcd_ep_t *ep)
 					 * a 0 length packet at the end. For Slave and
 					 * Buffer DMA modes in this case SW has
 					 * to initiate 2 transfers one with transfer size,
-					 * and the second with 0 size. For Desriptor
+					 * and the second with 0 size. For Descriptor
 					 * DMA mode SW is able to initiate a transfer,
 					 * which will handle all the packets including
-					 * the last  0 legth.
+					 * the last  0 length.
 					 */
 					ep->dwc_ep.sent_zlp = 0;
 					dwc_otg_ep_start_zl_transfer(core_if,
@@ -2447,10 +2447,10 @@ static void complete_ep(dwc_otg_pcd_ep_t *ep)
 					 * a 0 length packet at the end. For Slave and
 					 * Buffer DMA modes in this case SW has
 					 * to initiate 2 transfers one with transfer size,
-					 * and the second with 0 size. For Desriptor
+					 * and the second with 0 size. For Descriptor
 					 * DMA mode SW is able to initiate a transfer,
 					 * which will handle all the packets including
-					 * the last  0 legth.
+					 * the last  0 length.
 					 */
 					ep->dwc_ep.sent_zlp = 0;
 					dwc_otg_ep_start_zl_transfer(core_if,
@@ -2666,7 +2666,7 @@ static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if,
 
 				sts.d32 = dma_desc->status.d32;
 
-				/* Write status in iso_packet_decsriptor  */
+				/* Write status in iso_packet_descriptor  */
 				iso_packet->status =
 				    sts.b_iso_out.rxsts +
 				    (sts.b_iso_out.bs ^ BS_DMA_DONE);
@@ -2703,7 +2703,7 @@ static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if,
 
 			sts.d32 = dma_desc->status.d32;
 
-			/* Write status in iso_packet_decsriptor  */
+			/* Write status in iso_packet_descriptor  */
 			iso_packet->status =
 			    sts.b_iso_out.rxsts +
 			    (sts.b_iso_out.bs ^ BS_DMA_DONE);
@@ -2723,7 +2723,7 @@ static void set_ddma_iso_pkts_info(dwc_otg_core_if_t *core_if,
 
 		sts.d32 = dma_desc->status.d32;
 
-		/* Write status in iso_packet_decsriptor  */
+		/* Write status in iso_packet_descriptor  */
 		iso_packet->status =
 		    sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
 		if (iso_packet->status)
@@ -3186,7 +3186,7 @@ static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t *ep)
 /**
  * This function handles EP0 Control transfers.
  *
- * The state of the control tranfers are tracked in
+ * The state of the control transfers are tracked in
  * <code>ep0state</code>.
  */
 static void handle_ep0(dwc_otg_pcd_t *pcd)
@@ -3378,7 +3378,7 @@ static void restart_transfer(dwc_otg_pcd_t *pcd, const uint32_t epnum)
 
 
 /*
- * This function create new nextep sequnce based on Learn Queue.
+ * This function create new nextep sequence based on Learn Queue.
  *
  * @param core_if Programming view of DWC_otg controller
  */
@@ -3699,7 +3699,7 @@ static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t *pcd,
 
 	ep = get_in_ep(pcd, epnum);
 
-	/* Disable the NP Tx Fifo Empty Interrrupt */
+	/* Disable the NP Tx Fifo Empty Interrupt */
 	if (!core_if->dma_enable) {
 		intr_mask.b.nptxfempty = 1;
 		DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
@@ -3893,7 +3893,7 @@ do { \
 					   dev_global_regs->dtknqr4_fifoemptymsk);
 
 			DWC_DEBUGPL(DBG_PCDV,
-				    "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
+				    "IN EP INTERRUPT - %d\nempty_msk - %8x  diepctl - %8x\n",
 				    epnum, empty_msk, depctl.d32);
 
 			DWC_DEBUGPL(DBG_PCD,
@@ -3910,7 +3910,7 @@ do { \
 			/* Transfer complete */
 			if (diepint.b.xfercompl) {
 				/* Disable the NP Tx FIFO Empty
-				 * Interrrupt */
+				 * Interrupt */
 				if (core_if->en_multiple_tx_fifo == 0) {
 					intr_mask.b.nptxfempty = 1;
 					DWC_MODIFY_REG32
@@ -4076,7 +4076,7 @@ do { \
 					}
 				}
 			}
-			/* NAK Interrutp */
+			/* NAK Interrupt */
 			if (diepint.b.nak) {
 				DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
 					    epnum);
@@ -4577,7 +4577,7 @@ exit_xfercompl:
 					  epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
 				CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
 			}
-			/* Setup Phase Done (contorl EPs) */
+			/* Setup Phase Done (control EPs) */
 			if (doepint.b.setup) {
 #ifdef DEBUG_EP0
 				DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
@@ -4645,14 +4645,14 @@ exit_xfercompl:
 				CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
 			}
 
-			/* NAK Interrutp */
+			/* NAK Interrupt */
 			if (doepint.b.nak) {
 				DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
 				handle_out_ep_nak_intr(pcd, epnum);
 
 				CLEAR_OUT_EP_INTR(core_if, epnum, nak);
 			}
-			/* NYET Interrutp */
+			/* NYET Interrupt */
 			if (doepint.b.nyet) {
 				DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
 				handle_out_ep_nyet_intr(pcd, epnum);

drivers/usb/dwc_otg/310/dwc_otg_regs.h

@@ -942,7 +942,7 @@ typedef union glpmctl_data {
 		 * configures to drive the HSIC Idle state on the bus.
 		 * It then waits for the  device to initiate the Connect sequence.
 		 * In device mode once this bit is set, the device waits for
-		 * the HSIC Idle line state on the bus. Upon receving the Idle
+		 * the HSIC Idle line state on the bus. Upon receiving the Idle
 		 * line state, it initiates the HSIC Connect sequence.
 		 */
 		unsigned hsic_connect:1;
@@ -1312,7 +1312,7 @@ typedef union doepint_data {
 		unsigned epdisabled:1;
 		/** AHB Error */
 		unsigned ahberr:1;
-		/** Setup Phase Done (contorl EPs) */
+		/** Setup Phase Done (control EPs) */
 		unsigned setup:1;
 		/** OUT Token Received when Endpoint Disabled */
 		unsigned outtknepdis:1;
@@ -1803,8 +1803,8 @@ typedef struct dwc_otg_dev_if {
 
 	/* Device configuration information */
 	uint8_t speed;				 /**< Device Speed	0: Unknown, 1: LS, 2:FS, 3: HS */
-	uint8_t num_in_eps;		 /**< Number # of Tx EP range: 0-15 exept ep0 */
-	uint8_t num_out_eps;		 /**< Number # of Rx EP range: 0-15 exept ep 0*/
+	uint8_t num_in_eps;		 /**< Number # of Tx EP range: 0-15 except ep0 */
+	uint8_t num_out_eps;		 /**< Number # of Rx EP range: 0-15 except ep 0*/
 
 	/** Size of periodic FIFOs (Bytes) */
 	uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];