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lcd: A311D2 vbyone parameter modify [1/1]

Browse Source 
PD#SWPL-108218

Problem:
a311d2 eye pattern failed

Solution:
modify parameter

Verify:
t7c

Change-Id: Icea84ab88bc8b2f5d1c837a71f8a238001eded40
Signed-off-by: lizhi.hu <lizhi.hu@amlogic.com>
This commit is contained in:
lizhi.hu
2023-01-11 15:48:52 +08:00
committed by gerrit autosubmit
parent 798916e7c0
commit d3535ac8a3
2 changed files with 23 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/mesont7_an400-panel.dtsi
+13 -13
View File
@@ -73,7 +73,7 @@
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0x3 0>; /*vswing_level, preem_level*/
phy_attr=<0x8 0xf>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
@@ -117,7 +117,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -162,7 +162,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -207,7 +207,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -252,7 +252,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -297,7 +297,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -889,7 +889,7 @@
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0x3 0>; /*vswing_level, preem_level*/
phy_attr=<0x8 0xf>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
@@ -933,7 +933,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -978,7 +978,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -1023,7 +1023,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -1068,7 +1068,7 @@
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0x7 1>; /* vswing_level, preem_level */
phy_attr=<0x8 0xf>; /* vswing_level, preem_level */
hw_filter=<0 0>; /* filter_time, filter_cnt*/
/* power step: type, index, value, delay(ms) */
@@ -1360,7 +1360,7 @@
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0x3 0>; /*vswing_level, preem_level*/
phy_attr=<0x8 0xf>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
@@ -1402,7 +1402,7 @@
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0x3 0>; /*vswing_level, preem_level*/
phy_attr=<0x8 0xf>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
drivers/media/vout/lcd/lcd_phy_config.c
+10 -6
View File
@@ -772,7 +772,8 @@ static void lcd_lvds_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
}
if (status) {
if (lcd_phy_ctrl->lane_lock & flag) {
if ((lcd_phy_ctrl->lane_lock & flag) &&
((lcd_phy_ctrl->lane_lock & flag) != flag)) {
LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
lcd_phy_ctrl->lane_lock, flag);
return;
@@ -786,7 +787,7 @@ static void lcd_lvds_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
phy->vswing_level, phy->preem_level);
}
data_lane0_aux = 0x16430028;
data_lane0_aux = 0x06430028 | (phy->preem_level << 28);
data_lane1_aux = 0x0100ffff;
data_lane = 0x06530028 | (phy->preem_level << 28);
lcd_phy_cntl_set_t7(flag, data_lane0_aux, data_lane1_aux, data_lane);
@@ -830,7 +831,8 @@ static void lcd_vbyone_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
}
if (status) {
if (lcd_phy_ctrl->lane_lock & flag) {
if ((lcd_phy_ctrl->lane_lock & flag) &&
((lcd_phy_ctrl->lane_lock & flag) != flag)) {
LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
lcd_phy_ctrl->lane_lock, flag);
return;
@@ -844,7 +846,7 @@ static void lcd_vbyone_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
phy->vswing_level, phy->preem_level);
}
data_lane0_aux = 0x26430028;
data_lane0_aux = 0x06430028 | (phy->preem_level << 28);
data_lane1_aux = 0x0000ffff;
data_lane = 0x06530028 | (phy->preem_level << 28);
lcd_phy_cntl_set_t7(flag, data_lane0_aux, data_lane1_aux, data_lane);
@@ -887,7 +889,8 @@ static void lcd_mipi_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
}
if (status) {
if (lcd_phy_ctrl->lane_lock & flag) {
if ((lcd_phy_ctrl->lane_lock & flag) &&
((lcd_phy_ctrl->lane_lock & flag) != flag)) {
LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
lcd_phy_ctrl->lane_lock, flag);
return;
@@ -951,7 +954,8 @@ static void lcd_edp_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
}
if (status) {
if (lcd_phy_ctrl->lane_lock & flag) {
if ((lcd_phy_ctrl->lane_lock & flag) &&
((lcd_phy_ctrl->lane_lock & flag) != flag)) {
LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
lcd_phy_ctrl->lane_lock, flag);
return;