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https://github.com/hardkernel/kernel_common_drivers.git
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vpp: aisr demo mode sr error [1/1]
PD#SWPL-238490 Problem: aisr demo mode sr error Solution: change reg addr error Verify: t6x Change-Id: Ic08eae7856cbc3d0f378bc4f5bc853850cd67317 Signed-off-by: hai.cao <hai.cao@amlogic.com>
This commit is contained in:
committed by
gerrit autosubmit
parent
8139cd4ae3
commit
d522fa1821
@@ -18996,9 +18996,15 @@ int get_video_reg_table(u32 *check_item)
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}
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}
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if (cur_dev->inline_aisr_support) {
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memcpy(check_item,
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&t6w_aisr_demo_reg,
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sizeof(struct hw_aisr_demo_reg_s));
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if (video_is_meson_t6w_cpu()) {
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memcpy(check_item,
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&t6w_aisr_demo_reg,
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sizeof(struct hw_aisr_demo_reg_s));
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} else if (video_is_meson_t6x_cpu()) {
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memcpy(check_item,
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&t6x_aisr_demo_reg,
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sizeof(struct hw_aisr_demo_reg_s));
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}
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vd_reg_cnt += sizeof(struct hw_aisr_demo_reg_s) / sizeof(u32);
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check_item += sizeof(struct hw_aisr_demo_reg_s) / sizeof(u32);
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}
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@@ -19309,10 +19315,17 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo)
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sizeof(struct hw_vsr_safa_nonlinear_reg_s));
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}
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}
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if (cur_dev->inline_aisr_support)
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memcpy(&cur_dev->aisr_demo_mode_reg,
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&t6w_aisr_demo_reg,
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sizeof(struct hw_aisr_demo_reg_s));
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if (cur_dev->inline_aisr_support) {
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if (video_is_meson_t6w_cpu()) {
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memcpy(&cur_dev->aisr_demo_mode_reg,
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&t6w_aisr_demo_reg,
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sizeof(struct hw_aisr_demo_reg_s));
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} else if (video_is_meson_t6x_cpu()) {
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memcpy(&cur_dev->aisr_demo_mode_reg,
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&t6x_aisr_demo_reg,
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sizeof(struct hw_aisr_demo_reg_s));
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}
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}
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if (cur_dev->mosaic_support) {
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for (i = 0; i < SLICE_NUM; i++) {
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memcpy(&g_mosaic_frame[i].reg.vd_hw_vfcd_reg,
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@@ -1287,6 +1287,18 @@ struct hw_aisr_demo_reg_s t6w_aisr_demo_reg = {
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VPP_SR_DEBUG_DEMO_WND_COEF_0,
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};
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struct hw_aisr_demo_reg_s t6x_aisr_demo_reg = {
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VPP_PI_DEBUG_DEMO_WND_EN,
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VPP_PI_DEBUG_DEMO_WND_COEF_1,
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VPP_PI_DEBUG_DEMO_WND_COEF_0,
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T6W_SAFA_PPS_DEBUG_DEMO_EN,
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T6W_SAFA_PPS_DEBUG_DEMO_WND_COEF_1,
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T6W_SAFA_PPS_DEBUG_DEMO_WND_COEF_0,
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T6X_VPP_SR_DEBUG_DEMO_WND_EN,
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T6X_VPP_SR_DEBUG_DEMO_WND_COEF_1,
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T6X_VPP_SR_DEBUG_DEMO_WND_COEF_0,
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};
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struct hw_vsr_safa_nonlinear_reg_s vsr_safa_nonlinear_reg = {
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T6D_SAFA_PPS_HSC_REGION12_STARTP,
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T6D_SAFA_PPS_HSC_REGION34_STARTP,
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@@ -445,6 +445,7 @@ extern struct hw_vsr_safa_nonlinear_reg_s vsr_safa_nonlinear_reg_t6w;
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extern struct hw_vsr_safa_reg_s vsr_safa_reg_t6w;
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extern struct hw_aisr_demo_reg_s s7d_aisr_demo_reg;
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extern struct hw_aisr_demo_reg_s t6w_aisr_demo_reg;
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extern struct hw_aisr_demo_reg_s t6x_aisr_demo_reg;
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extern struct hw_mif_reg_s vd_mif_reg_t6w_array[MAX_VD_LAYER_G12];
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extern struct hw_vfcd_reg_s vd_vfcd_reg_t6w_array[MAX_VD_LAYER_G12];
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extern struct hw_fg_reg_s fg_reg_t6w_array[MAX_VD_LAYER_G12];
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@@ -663,6 +663,26 @@
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//Bit 15:12 reserved
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//Bit 11: 0 reg_debug_demo_wnd_0 // unsigned , RW,
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//default = 960 control debug window col size
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#define T6X_VPP_SR_DEBUG_DEMO_WND_EN 0x7a52
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//Bit 31: 8 reserved
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//Bit 7: 5 reserved
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//Bit 4 reg_sr_debug_demo_en // unsigned , RW, default = 0
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//Bit 3: 1 reserved
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//Bit 0 reg_sr_debug_demo_inverse // unsigned , RW, default = 0
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#define T6X_VPP_SR_DEBUG_DEMO_WND_COEF_1 0x7a53
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//Bit 31:28 reserved
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//Bit 27:16 reg_debug_demo_wnd_3 // unsigned , RW,
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//default = 2160 control debug window row size
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//Bit 15:12 reserved
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//Bit 11: 0 reg_debug_demo_wnd_2 // unsigned , RW,
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//default = 1920 ontrol debug window col size
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#define T6X_VPP_SR_DEBUG_DEMO_WND_COEF_0 0x7a54
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//Bit 31:28 reserved
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//Bit 27:16 reg_debug_demo_wnd_1 // unsigned , RW, default = 0
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//control debug window row size
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//Bit 15:12 reserved
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//Bit 11: 0 reg_debug_demo_wnd_0 // unsigned , RW, default = 0
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//control debug window col size
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#define SAFA_PPS_EDGE_AVGSTD_LUT2D_0_0 0x5142
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//Bit 31:30 reserved
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//Bit 29:24 reg_edge_avgstd_lut2d_0_6 // unsigned , RW, default = 0
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