vpp: aisr demo mode sr error [1/1]

PD#SWPL-238490

Problem:
aisr demo mode sr error

Solution:
change reg addr error

Verify:
t6x

Change-Id: Ic08eae7856cbc3d0f378bc4f5bc853850cd67317
Signed-off-by: hai.cao <hai.cao@amlogic.com>
This commit is contained in:
hai.cao
2025-11-05 16:31:57 +08:00
committed by gerrit autosubmit
parent 8139cd4ae3
commit d522fa1821
4 changed files with 53 additions and 7 deletions
+20 -7
View File
@@ -18996,9 +18996,15 @@ int get_video_reg_table(u32 *check_item)
}
}
if (cur_dev->inline_aisr_support) {
memcpy(check_item,
&t6w_aisr_demo_reg,
sizeof(struct hw_aisr_demo_reg_s));
if (video_is_meson_t6w_cpu()) {
memcpy(check_item,
&t6w_aisr_demo_reg,
sizeof(struct hw_aisr_demo_reg_s));
} else if (video_is_meson_t6x_cpu()) {
memcpy(check_item,
&t6x_aisr_demo_reg,
sizeof(struct hw_aisr_demo_reg_s));
}
vd_reg_cnt += sizeof(struct hw_aisr_demo_reg_s) / sizeof(u32);
check_item += sizeof(struct hw_aisr_demo_reg_s) / sizeof(u32);
}
@@ -19309,10 +19315,17 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo)
sizeof(struct hw_vsr_safa_nonlinear_reg_s));
}
}
if (cur_dev->inline_aisr_support)
memcpy(&cur_dev->aisr_demo_mode_reg,
&t6w_aisr_demo_reg,
sizeof(struct hw_aisr_demo_reg_s));
if (cur_dev->inline_aisr_support) {
if (video_is_meson_t6w_cpu()) {
memcpy(&cur_dev->aisr_demo_mode_reg,
&t6w_aisr_demo_reg,
sizeof(struct hw_aisr_demo_reg_s));
} else if (video_is_meson_t6x_cpu()) {
memcpy(&cur_dev->aisr_demo_mode_reg,
&t6x_aisr_demo_reg,
sizeof(struct hw_aisr_demo_reg_s));
}
}
if (cur_dev->mosaic_support) {
for (i = 0; i < SLICE_NUM; i++) {
memcpy(&g_mosaic_frame[i].reg.vd_hw_vfcd_reg,
+12
View File
@@ -1287,6 +1287,18 @@ struct hw_aisr_demo_reg_s t6w_aisr_demo_reg = {
VPP_SR_DEBUG_DEMO_WND_COEF_0,
};
struct hw_aisr_demo_reg_s t6x_aisr_demo_reg = {
VPP_PI_DEBUG_DEMO_WND_EN,
VPP_PI_DEBUG_DEMO_WND_COEF_1,
VPP_PI_DEBUG_DEMO_WND_COEF_0,
T6W_SAFA_PPS_DEBUG_DEMO_EN,
T6W_SAFA_PPS_DEBUG_DEMO_WND_COEF_1,
T6W_SAFA_PPS_DEBUG_DEMO_WND_COEF_0,
T6X_VPP_SR_DEBUG_DEMO_WND_EN,
T6X_VPP_SR_DEBUG_DEMO_WND_COEF_1,
T6X_VPP_SR_DEBUG_DEMO_WND_COEF_0,
};
struct hw_vsr_safa_nonlinear_reg_s vsr_safa_nonlinear_reg = {
T6D_SAFA_PPS_HSC_REGION12_STARTP,
T6D_SAFA_PPS_HSC_REGION34_STARTP,
+1
View File
@@ -445,6 +445,7 @@ extern struct hw_vsr_safa_nonlinear_reg_s vsr_safa_nonlinear_reg_t6w;
extern struct hw_vsr_safa_reg_s vsr_safa_reg_t6w;
extern struct hw_aisr_demo_reg_s s7d_aisr_demo_reg;
extern struct hw_aisr_demo_reg_s t6w_aisr_demo_reg;
extern struct hw_aisr_demo_reg_s t6x_aisr_demo_reg;
extern struct hw_mif_reg_s vd_mif_reg_t6w_array[MAX_VD_LAYER_G12];
extern struct hw_vfcd_reg_s vd_vfcd_reg_t6w_array[MAX_VD_LAYER_G12];
extern struct hw_fg_reg_s fg_reg_t6w_array[MAX_VD_LAYER_G12];
+20
View File
@@ -663,6 +663,26 @@
//Bit 15:12 reserved
//Bit 11: 0 reg_debug_demo_wnd_0 // unsigned , RW,
//default = 960 control debug window col size
#define T6X_VPP_SR_DEBUG_DEMO_WND_EN 0x7a52
//Bit 31: 8 reserved
//Bit 7: 5 reserved
//Bit 4 reg_sr_debug_demo_en // unsigned , RW, default = 0
//Bit 3: 1 reserved
//Bit 0 reg_sr_debug_demo_inverse // unsigned , RW, default = 0
#define T6X_VPP_SR_DEBUG_DEMO_WND_COEF_1 0x7a53
//Bit 31:28 reserved
//Bit 27:16 reg_debug_demo_wnd_3 // unsigned , RW,
//default = 2160 control debug window row size
//Bit 15:12 reserved
//Bit 11: 0 reg_debug_demo_wnd_2 // unsigned , RW,
//default = 1920 ontrol debug window col size
#define T6X_VPP_SR_DEBUG_DEMO_WND_COEF_0 0x7a54
//Bit 31:28 reserved
//Bit 27:16 reg_debug_demo_wnd_1 // unsigned , RW, default = 0
//control debug window row size
//Bit 15:12 reserved
//Bit 11: 0 reg_debug_demo_wnd_0 // unsigned , RW, default = 0
//control debug window col size
#define SAFA_PPS_EDGE_AVGSTD_LUT2D_0_0 0x5142
//Bit 31:30 reserved
//Bit 29:24 reg_edge_avgstd_lut2d_0_6 // unsigned , RW, default = 0