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vpp: recovery video set when vpu power closed in STR [1/1]

Browse Source 
PD#SWPL-160995

Problem:
recovery video set when vpu power closed in STR

Solution:
recovery video set when vpu power closed in STR

Verify:
s7

Change-Id: Icb8083923e2e104a5106a55e8dfc9ade7087b18a
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
This commit is contained in:
Pengcheng Chen
2024-03-14 19:35:08 +08:00
committed by gerrit autosubmit
parent cf15989a9f
commit d85f2d481f
5 changed files with 415 additions and 345 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/osd/osd_hw.c
+283 -252
View File
@@ -14698,10 +14698,285 @@ static void osd_flag_regs_init(void)
osd_rdma_flag_init();
}
static void osd_hw_init(u32 logo_loaded)
{
u32 idx, data32;
osd_vpu_power_on();
osd_flag_regs_init();
/*close gamma only for axg*/
if (osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE)
osd_reg_write(L_GAMMA_CNTL_PORT, 0);
/* here we will init default value ,these value only set once . */
if (!logo_loaded) {
if (osd_dev_hw.s5_display)
s5_default_path_settings();
if (osd_dev_hw.multi_afbc_core)
multi_afbc_default_path_setting();
/* init vpu fifo control register */
if (osd_dev_hw.display_type != C3_DISPLAY) {
data32 = osd_reg_read(VPP_OFIFO_SIZE);
if (osd_hw.osd_meson_dev.osd_ver >= OSD_HIGH_ONE) {
data32 &= ~((0xfff << 20) | 0x3fff);
data32 |= (osd_hw.osd_meson_dev.vpp_fifo_len) << 20;
data32 |= osd_hw.osd_meson_dev.vpp_fifo_len + 1;
} else {
data32 |= osd_hw.osd_meson_dev.vpp_fifo_len;
}
osd_reg_write(VPP_OFIFO_SIZE, data32);
data32 = 0x08080808;
osd_reg_write(VPP_HOLD_LINES, data32);
}
/* init osd fifo control register
* set DDR request priority to be urgent
*/
data32 = 1;
/* hold_fifo_lines */
if (osd_hw.osd_meson_dev.osd_ver >= OSD_HIGH_ONE)
data32 |= VIU1_DEFAULT_HOLD_LINE << 5;
else
data32 |= MIN_HOLD_LINE << 5;
/* burst_len_sel: 3=64, g12a = 5 */
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE ||
osd_dev_hw.display_type == C3_DISPLAY) {
data32 |= 1 << 10;
data32 |= 1 << 31;
} else {
data32 |= 3 << 10;
}
/*
* bit 23:22, fifo_ctrl
* 00 : for 1 word in 1 burst
* 01 : for 2 words in 1 burst
* 10 : for 4 words in 1 burst
* 11 : reserved
*/
data32 |= 2 << 22;
/* bit 28:24, fifo_lim */
data32 |= 2 << 24;
/* data32_ = data32; */
/* fifo_depth_val: 32 or 64 *8 = 256 or 512 */
data32 |= (osd_hw.osd_meson_dev.osd_fifo_len
& 0xfffffff) << 12;
for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++)
osd_reg_write(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
data32);
/* osd_reg_write(VIU_OSD2_FIFO_CTRL_STAT, data32_); */
if (osd_dev_hw.display_type != C3_DISPLAY) {
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_S1A)
osd_reg_clr_mask(VPP_MISC, VPP_VD1_POSTBLEND);
osd_reg_set_mask(VPP_MISC, VPP_POSTBLEND_EN);
osd_reg_clr_mask(VPP_MISC, VPP_PREBLEND_EN);
if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL) {
osd_vpp_misc =
osd_reg_read(VPP_MISC) & OSD_RELATIVE_BITS;
osd_vpp_misc &=
~(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND);
notify_to_amvideo();
osd_reg_clr_mask(VPP_MISC,
VPP_OSD1_POSTBLEND |
VPP_OSD2_POSTBLEND);
}
}
/* just disable osd to avoid booting hang up */
data32 = 0x1 << 0;
data32 |= OSD_GLOBAL_ALPHA_DEF << 12;
for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++)
osd_reg_write(hw_osd_reg_array[idx].osd_ctrl_stat,
data32);
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE)
osd_setting_default_hwc();
}
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_T7) {
osd_mali_afbcd_top_ctrl =
osd_reg_read(MALI_AFBCD_TOP_CTRL) & osd_mali_afbcd_top_ctrl_mask;
osd_mali_afbcd_top_ctrl |= 1 << 19;
osd_mali_afbcd_top_ctrl &= ~(1 << 15);
osd_mali_afbcd_top_ctrl &= ~(1 << 20);
osd_mali_afbcd1_top_ctrl =
osd_reg_read(MALI_AFBCD1_TOP_CTRL) & osd_mali_afbcd1_top_ctrl_mask;
osd_mali_afbcd1_top_ctrl &= ~(1 << 20);
notify_to_amdv();
}
if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL &&
osd_dev_hw.display_type != C3_DISPLAY) {
osd_vpp_misc =
osd_reg_read(VPP_MISC) & OSD_RELATIVE_BITS;
if (osd_hw.hw_cursor_en) {
osd_vpp_misc |= (VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
notify_to_amvideo();
osd_reg_set_mask(VPP_MISC,
VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
osd_hw.order[OSD1] = OSD_ORDER_10;
} else {
osd_vpp_misc &= ~(VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
notify_to_amvideo();
osd_reg_clr_mask(VPP_MISC,
VPP_POST_FG_OSD2 |
VPP_PRE_FG_OSD2);
osd_hw.order[OSD1] = OSD_ORDER_01;
}
} else if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count; idx++) {
if (idx < osd_hw.osd_meson_dev.viu1_osd_count) {
/* TODO: temp set at here,
* need move it to uboot
*/
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
1, 31, 1);
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
1, 10, 2);
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
VIU1_DEFAULT_HOLD_LINE, 5, 5);
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_G12B)
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_ctrl_stat,
1, 0, 1);
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_ctrl_stat,
0, 31, 1);
osd_hw.powered[idx] = 1;
} else {
osd_hw.powered[idx] = 0;
}
osd_set_deband(idx, osd_hw.osd_deband_enable[idx]);
}
osd_set_basic_urgent(true);
if (osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_TXHD2 &&
osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_S1A &&
osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_S7 &&
osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_T7)
osd_set_two_ports(true);
if (osd_dev_hw.prevsync_support) {
u32 vpp0_pre_go_field = 0;
u32 vpp0_post_go_field = 3;
u32 output_index;
/* for t3 0: vpp0_pre_go_field, 3: vpp0_post_go_field */
if (is_meson_rev_a()) {
osd_set_vpp_path_default(VPP_OSD1, vpp0_pre_go_field);
osd_set_vpp_path_default(VPP_OSD2, vpp0_pre_go_field);
if (osd_hw.osd_meson_dev.osd_count > OSD3) {
output_index = get_output_device_id(OSD3);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD3,
vpp0_pre_go_field);
else
osd_set_vpp_path_default(VPP_OSD3,
output_index);
}
if (osd_hw.osd_meson_dev.osd_count > OSD4) {
output_index = get_output_device_id(OSD4);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD4,
vpp0_pre_go_field);
else
osd_set_vpp_path_default(VPP_OSD4,
output_index);
}
} else {
osd_set_vpp_path_default(VPP_OSD1, vpp0_post_go_field);
osd_set_vpp_path_default(VPP_OSD2, vpp0_post_go_field);
if (osd_hw.osd_meson_dev.osd_count > OSD3) {
output_index = get_output_device_id(OSD3);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD3,
vpp0_post_go_field);
else
osd_set_vpp_path_default(VPP_OSD3,
output_index);
}
if (osd_hw.osd_meson_dev.osd_count > OSD4) {
output_index = get_output_device_id(OSD4);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD4,
vpp0_post_go_field);
else
osd_set_vpp_path_default(VPP_OSD4,
output_index);
}
}
} else {
/* for t7 0: vpp0_post_go_field, no pre go field */
if (osd_hw.osd_meson_dev.osd_count > OSD3)
osd_set_vpp_path_default(VPP_OSD3,
get_output_device_id(OSD3));
if (osd_hw.osd_meson_dev.osd_count > OSD4)
osd_set_vpp_path_default(VPP_OSD4,
get_output_device_id(OSD4));
}
}
/* disable deband as default */
if (osd_hw.osd_meson_dev.has_deband) {
if (osd_dev_hw.display_type != C3_DISPLAY)
osd_reg_write(OSD_DB_FLT_CTRL, 0);
else
osd_reg_write(VOUT_OSD1_DB_FLT_CTRL, 0);
}
if (osd_hw.osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_AXG) {
data32 = osd_reg_read
(hw_osd_reg_array[OSD1].osd_fifo_ctrl_stat);
/* bit[9:5]: HOLD_FIFO_LINES */
data32 &= ~(0x1f << 5);
data32 |= 0x18 << 5;
osd_reg_write(hw_osd_reg_array[OSD1].osd_fifo_ctrl_stat,
data32);
}
if (osd_hw.osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_TXHD2 &&
osd_hw.osd_meson_dev.has_vpp1) {
set_vpp_osd1_rgb2yuv(1);
set_vpp_osd2_rgb2yuv(0);
} else if (osd_hw.osd_meson_dev.osd_rgb2yuv == 1) {
set_vpp_osd1_rgb2yuv(1);
set_vpp_osd2_rgb2yuv(1);
}
if (osd_dev_hw.display_type == C3_DISPLAY &&
osd_hw.osd_meson_dev.osd_rgb2yuv)
osd1_matrix_yuv2rgb(RGB2YUV);
if (osd_hw.hw_rdma_en) {
osd_rdma_enable(VPU_VPP0, 2);
if (osd_hw.osd_meson_dev.has_vpp1 &&
osd_hw.display_dev_cnt == 2)
osd_rdma_enable(VPU_VPP1, 2);
if (osd_hw.osd_meson_dev.has_vpp2 &&
osd_hw.display_dev_cnt == 3)
osd_rdma_enable(VPU_VPP2, 2);
} else {
osd_hw.afbc_force_reset = 0;
}
/* temp set */
for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++) {
osd_hw.use_h_filter_mode[idx] = 0xff;
osd_hw.use_v_filter_mode[idx] = 0xff;
osd_update_coef(idx);
}
}
void osd_init_hw(u32 logo_loaded, u32 osd_probe,
struct osd_device_data_s *osd_meson)
{
u32 idx, data32;
u32 idx;
int err_num = 0;
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
void *osd_secure_op[VPP_TOP_MAX] = {VSYNCOSD_WR_MPEG_REG_BITS,
@@ -14724,7 +14999,6 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
osd_hw.vpp_num++;
if (osd_hw.osd_meson_dev.has_vpp2)
osd_hw.vpp_num++;
osd_vpu_power_on();
#ifndef CONFIG_AMLOGIC_C3_REMOVE
if (osd_meson->cpu_id == __MESON_CPU_MAJOR_ID_S5 ||
@@ -14821,7 +15095,6 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
if (osd_dev_hw.display_type == C3_DISPLAY)
irq_clr_c3();
osd_flag_regs_init();
recovery_regs_init();
/* set osd vpp rdma func */
@@ -14845,125 +15118,8 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
}
if (osd_hw.osd_meson_dev.has_rdma)
osd_hw.hw_rdma_en = 1;
/*close gamma only for axg*/
if (osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE)
osd_reg_write(L_GAMMA_CNTL_PORT, 0);
/* here we will init default value ,these value only set once . */
if (!logo_loaded) {
if (osd_dev_hw.s5_display)
s5_default_path_settings();
if (osd_dev_hw.multi_afbc_core)
multi_afbc_default_path_setting();
/* init vpu fifo control register */
if (osd_dev_hw.display_type != C3_DISPLAY) {
data32 = osd_reg_read(VPP_OFIFO_SIZE);
if (osd_hw.osd_meson_dev.osd_ver >= OSD_HIGH_ONE) {
data32 &= ~((0xfff << 20) | 0x3fff);
data32 |= (osd_hw.osd_meson_dev.vpp_fifo_len) << 20;
data32 |= osd_hw.osd_meson_dev.vpp_fifo_len + 1;
} else {
data32 |= osd_hw.osd_meson_dev.vpp_fifo_len;
}
osd_reg_write(VPP_OFIFO_SIZE, data32);
data32 = 0x08080808;
osd_reg_write(VPP_HOLD_LINES, data32);
}
/* init osd fifo control register
* set DDR request priority to be urgent
*/
data32 = 1;
/* hold_fifo_lines */
if (osd_hw.osd_meson_dev.osd_ver >= OSD_HIGH_ONE)
data32 |= VIU1_DEFAULT_HOLD_LINE << 5;
else
data32 |= MIN_HOLD_LINE << 5;
/* burst_len_sel: 3=64, g12a = 5 */
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE ||
osd_dev_hw.display_type == C3_DISPLAY) {
data32 |= 1 << 10;
data32 |= 1 << 31;
} else {
data32 |= 3 << 10;
}
/*
* bit 23:22, fifo_ctrl
* 00 : for 1 word in 1 burst
* 01 : for 2 words in 1 burst
* 10 : for 4 words in 1 burst
* 11 : reserved
*/
data32 |= 2 << 22;
/* bit 28:24, fifo_lim */
data32 |= 2 << 24;
/* data32_ = data32; */
/* fifo_depth_val: 32 or 64 *8 = 256 or 512 */
data32 |= (osd_hw.osd_meson_dev.osd_fifo_len
& 0xfffffff) << 12;
for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++)
osd_reg_write(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
data32);
/* osd_reg_write(VIU_OSD2_FIFO_CTRL_STAT, data32_); */
if (osd_dev_hw.display_type != C3_DISPLAY) {
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_S1A)
osd_reg_clr_mask(VPP_MISC, VPP_VD1_POSTBLEND);
osd_reg_set_mask(VPP_MISC, VPP_POSTBLEND_EN);
osd_reg_clr_mask(VPP_MISC, VPP_PREBLEND_EN);
if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL) {
osd_vpp_misc =
osd_reg_read(VPP_MISC) & OSD_RELATIVE_BITS;
osd_vpp_misc &=
~(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND);
notify_to_amvideo();
osd_reg_clr_mask(VPP_MISC,
VPP_OSD1_POSTBLEND |
VPP_OSD2_POSTBLEND);
}
}
/* just disable osd to avoid booting hang up */
data32 = 0x1 << 0;
data32 |= OSD_GLOBAL_ALPHA_DEF << 12;
for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++)
osd_reg_write(hw_osd_reg_array[idx].osd_ctrl_stat,
data32);
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE)
osd_setting_default_hwc();
} else if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_T7) {
osd_mali_afbcd_top_ctrl =
osd_reg_read(MALI_AFBCD_TOP_CTRL) & osd_mali_afbcd_top_ctrl_mask;
osd_mali_afbcd_top_ctrl |= 1 << 19;
osd_mali_afbcd_top_ctrl &= ~(1 << 15);
osd_mali_afbcd_top_ctrl &= ~(1 << 20);
osd_mali_afbcd1_top_ctrl =
osd_reg_read(MALI_AFBCD1_TOP_CTRL) & osd_mali_afbcd1_top_ctrl_mask;
osd_mali_afbcd1_top_ctrl &= ~(1 << 20);
notify_to_amdv();
}
if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL &&
osd_dev_hw.display_type != C3_DISPLAY) {
osd_vpp_misc =
osd_reg_read(VPP_MISC) & OSD_RELATIVE_BITS;
if (osd_hw.hw_cursor_en) {
osd_vpp_misc |= (VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
notify_to_amvideo();
osd_reg_set_mask(VPP_MISC,
VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
osd_hw.order[OSD1] = OSD_ORDER_10;
} else {
osd_vpp_misc &= ~(VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
notify_to_amvideo();
osd_reg_clr_mask(VPP_MISC,
VPP_POST_FG_OSD2 |
VPP_PRE_FG_OSD2);
osd_hw.order[OSD1] = OSD_ORDER_01;
}
} else if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
osd_hw.order[OSD1] = LAYER_1;
osd_hw.order[OSD2] = LAYER_2;
osd_hw.order[OSD3] = LAYER_3;
@@ -14992,116 +15148,15 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
MALI_AFBC_32X8_PIXEL << 1 |
MALI_AFBC_SPLIT_ON;
osd_hw.osd_afbcd[idx].afbc_start = 0;
osd_hw.osd_afbcd[idx].out_addr_id = idx + 1;
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_G12A) {
osd_hw.afbc_force_reset = 1;
osd_hw.afbc_regs_backup = 1;
}
if (idx < osd_hw.osd_meson_dev.viu1_osd_count) {
/* TODO: temp set at here,
* need move it to uboot
*/
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
1, 31, 1);
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
1, 10, 2);
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_fifo_ctrl_stat,
VIU1_DEFAULT_HOLD_LINE, 5, 5);
if (osd_hw.osd_meson_dev.cpu_id ==
__MESON_CPU_MAJOR_ID_G12B)
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_ctrl_stat,
1, 0, 1);
osd_reg_set_bits
(hw_osd_reg_array[idx].osd_ctrl_stat,
0, 31, 1);
osd_hw.powered[idx] = 1;
} else {
osd_hw.powered[idx] = 0;
}
}
osd_set_basic_urgent(true);
if (osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_TXHD2 &&
osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_S1A &&
osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_S7 &&
osd_hw.osd_meson_dev.cpu_id !=
__MESON_CPU_MAJOR_ID_T7)
osd_set_two_ports(true);
if (osd_dev_hw.prevsync_support) {
u32 vpp0_pre_go_field = 0;
u32 vpp0_post_go_field = 3;
u32 output_index;
/* for t3 0: vpp0_pre_go_field, 3: vpp0_post_go_field */
if (is_meson_rev_a()) {
osd_set_vpp_path_default(VPP_OSD1, vpp0_pre_go_field);
osd_set_vpp_path_default(VPP_OSD2, vpp0_pre_go_field);
if (osd_hw.osd_meson_dev.osd_count > OSD3) {
output_index = get_output_device_id(OSD3);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD3,
vpp0_pre_go_field);
else
osd_set_vpp_path_default(VPP_OSD3,
output_index);
}
if (osd_hw.osd_meson_dev.osd_count > OSD4) {
output_index = get_output_device_id(OSD4);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD4,
vpp0_pre_go_field);
else
osd_set_vpp_path_default(VPP_OSD4,
output_index);
}
} else {
osd_set_vpp_path_default(VPP_OSD1, vpp0_post_go_field);
osd_set_vpp_path_default(VPP_OSD2, vpp0_post_go_field);
if (osd_hw.osd_meson_dev.osd_count > OSD3) {
output_index = get_output_device_id(OSD3);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD3,
vpp0_post_go_field);
else
osd_set_vpp_path_default(VPP_OSD3,
output_index);
}
if (osd_hw.osd_meson_dev.osd_count > OSD4) {
output_index = get_output_device_id(OSD4);
if (output_index == VIU1)
osd_set_vpp_path_default(VPP_OSD4,
vpp0_post_go_field);
else
osd_set_vpp_path_default(VPP_OSD4,
output_index);
}
}
} else {
/* for t7 0: vpp0_post_go_field, no pre go field */
if (osd_hw.osd_meson_dev.osd_count > OSD3)
osd_set_vpp_path_default(VPP_OSD3,
get_output_device_id(OSD3));
if (osd_hw.osd_meson_dev.osd_count > OSD4)
osd_set_vpp_path_default(VPP_OSD4,
get_output_device_id(OSD4));
}
}
/* disable deband as default */
if (osd_hw.osd_meson_dev.has_deband) {
if (osd_dev_hw.display_type != C3_DISPLAY)
osd_reg_write(OSD_DB_FLT_CTRL, 0);
else
osd_reg_write(VOUT_OSD1_DB_FLT_CTRL, 0);
}
for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count; idx++) {
osd_hw.updated[idx] = 0;
osd_hw.urgent[idx] = 1;
@@ -15155,12 +15210,12 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
* osd_hw.rotation_pandata[idx].y_start = 0;
*/
osd_set_dummy_data(idx, 0xff);
osd_set_deband(idx, osd_hw.osd_deband_enable[idx]);
#ifdef DEBUG_FIRSTFRAME
set_force_dimm(idx);
set_force_save_frames(idx);
#endif
}
osd_hw_init(logo_loaded);
/* hwc_enable == 0 handler */
#ifdef CONFIG_AMLOGIC_MEDIA_FB_OSD_SYNC_FENCE
osd_hw.osd_fence[VIU1][DISABLE].sync_fence_handler =
@@ -15200,23 +15255,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
osd_hw.osd_preblend_en = 0;
osd_hw.fix_target_width = 1920;
osd_hw.fix_target_height = 1080;
if (osd_hw.osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_AXG) {
data32 = osd_reg_read
(hw_osd_reg_array[OSD1].osd_fifo_ctrl_stat);
/* bit[9:5]: HOLD_FIFO_LINES */
data32 &= ~(0x1f << 5);
data32 |= 0x18 << 5;
osd_reg_write(hw_osd_reg_array[OSD1].osd_fifo_ctrl_stat,
data32);
}
if (osd_hw.osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_TXHD2 &&
osd_hw.osd_meson_dev.has_vpp1) {
set_vpp_osd1_rgb2yuv(1);
set_vpp_osd2_rgb2yuv(0);
} else if (osd_hw.osd_meson_dev.osd_rgb2yuv == 1) {
set_vpp_osd1_rgb2yuv(1);
set_vpp_osd2_rgb2yuv(1);
}
if (osd_hw.fb_drvier_probe) {
#ifdef CONFIG_AMLOGIC_MEDIA_FB_OSD_SYNC_FENCE
INIT_LIST_HEAD(&post_fence_list[VIU1]);
@@ -15260,17 +15299,6 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
request_fiq(INT_VIU_VSYNC, &osd_viu2_fiq_isr);
#endif
}
if (osd_hw.hw_rdma_en) {
osd_rdma_enable(VPU_VPP0, 2);
if (osd_hw.osd_meson_dev.has_vpp1 &&
osd_hw.display_dev_cnt == 2)
osd_rdma_enable(VPU_VPP1, 2);
if (osd_hw.osd_meson_dev.has_vpp2 &&
osd_hw.display_dev_cnt == 3)
osd_rdma_enable(VPU_VPP2, 2);
} else {
osd_hw.afbc_force_reset = 0;
}
#ifdef CONFIG_AMLOGIC_MEDIA_FB_OSD_SYNC_FENCE
affinity_set_init();
#endif
@@ -15764,6 +15792,9 @@ void osd_suspend_hw(void)
void osd_resume_hw(void)
{
/* for hw reg recovery */
osd_hw_init(0);
if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL &&
osd_dev_hw.display_type != C3_DISPLAY) {
if (osd_hw.reg_status_save &
drivers/media/video_sink/video.c
+1
View File
@@ -13773,6 +13773,7 @@ static void video_early_suspend(struct early_suspend *h)
static void video_late_resume(struct early_suspend *h)
{
video_resume_hw_recovery();
video_suspend_cycle = 0;
video_suspend = false;
log_out = 1;
drivers/media/video_sink/video_hw.c
+114 -86
View File
@@ -13421,25 +13421,14 @@ void vd1_set_go_field(void)
}
}
int video_hw_init(void)
static int _video_hw_init(void)
{
u32 cur_hold_line, ofifo_size;
#ifdef CONFIG_AMLOGIC_VPU
struct vpu_dev_s *arb_vpu_dev;
#endif
int i;
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
void *video_secure_op[VPP_TOP_MAX] = {VSYNC_WR_MPEG_REG_BITS,
VSYNC_WR_MPEG_REG_BITS_VPP1,
VSYNC_WR_MPEG_REG_BITS_VPP2,
PRE_VSYNC_WR_MPEG_REG_BITS};
#endif
u32 ofifo_size;
if (cur_dev->display_module == C3_DISPLAY_MODULE) {
video_hw_init_c3();
return 0;
}
if (!legacy_vpp) {
if (vpp_ofifo_size == 0xff)
ofifo_size = 0x1000;
@@ -13476,7 +13465,7 @@ int video_hw_init(void)
WRITE_VCBUS_REG_BITS(VIU_MISC_CTRL1, 0xff, 16, 8);
WRITE_VCBUS_REG(VPP_AMDV_CTRL, 0x22000);
/*
*default setting is black for dummy data1& dump data0,
*default setting is black for dummy data1& dummy data0,
*for dummy data1 the y/cb/cr data width is 10bit on gxm,
*for dummy data the y/cb/cr data width is 8bit but
*vpp_dummy_data will be left shift 2bit auto on gxm!!!
@@ -13514,6 +13503,102 @@ int video_hw_init(void)
di_used_vd1_afbc(false);
}
/*disable sr default when power up*/
if (cur_dev->display_module != C3_DISPLAY_MODULE) {
WRITE_VCBUS_REG(VPP_SRSHARP0_CTRL, 0);
WRITE_VCBUS_REG(VPP_SRSHARP1_CTRL, 0);
}
/* disable aisr_sr1_nn func */
if (cur_dev->aisr_support)
aisr_sr1_nn_enable(0);
/* Temp force set dmc */
if (!legacy_vpp) {
if (cur_dev->display_module == OLD_DISPLAY_MODULE ||
video_is_meson_t5w_cpu())
WRITE_DMCREG
(DMC_AM0_CHAN_CTRL,
0x8ff403cf);
if (video_is_meson_t5m_cpu())
WRITE_VCBUS_REG(VPU_RDARB_UGT_L2C1, 0xffff);
/* for vd1 & vd2 dummy alpha*/
WRITE_VCBUS_REG
(VPP_POST_BLEND_DUMMY_ALPHA,
0x7fffffff);
WRITE_VCBUS_REG_BITS
(VPP_MISC1, 0x100, 0, 9);
}
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
/* disable latch for sr core0/1 scaler */
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 0, 1);
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 8, 1);
WRITE_VCBUS_REG_BITS
(sr_info.sr1_sharp_sync_ctrl,
1, 8, 1);
if (cur_dev->aisr_support)
WRITE_VCBUS_REG_BITS
(sr_info.sr1_sharp_sync_ctrl,
1, 17, 1);
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 0, 1);
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 8, 1);
}
/* force bypass dolby for TL1/T5, no dolby function */
if (!glayer_info[0].dv_support && !is_meson_s4d_cpu())
WRITE_VCBUS_REG_BITS(AMDV_PATH_CTRL, 0xf, 0, 6);
if (video_is_meson_t7_cpu()) {
/* vpu port map for t7 */
/* vpp_arb0: osd1, vd1, osd3, dolby0, vd3 */
/* vpp_arb1: osd2, vd2, osd4, mali-afbc */
/* arb rd0: vpp_arb0, rdma read, ldim, vdin_afbce, vpu dma */
/* arb rd2: vpp_arb1, */
/* VPU[0x3978]=0x0aa00000 */
/* VPU[0x279d]=0x00900000 */
/*
*setting move to vpu arb driver init
*WRITE_VCBUS_REG(VPU_RDARB_UGT_L2C1, 0xffff);
*/
} else if (video_is_meson_t5m_cpu()) {
/* vpu port map for t5m */
/* vpp_arb0: vd1, vd2, dolby0 */
/* vpp_arb1: osd1, osd2, osd3, mali-afbc */
/* arb rd0: vpp_arb0, rdma read, vpu sub, dcntr, tcon p2 */
/* arb rd2: vpp_arb1, tcon p1 */
/* VPU[0x3978]=0x0b300000 */
/* VPU[0x279d]=0x00920000 */
/* vpp_arb0, vpp_arb1 super urgent */
WRITE_VCBUS_REG(VPU_RDARB_UGT_L2C1, 0xffff);
}
vd_set_go_field_default();
return 0;
}
int video_hw_init(void)
{
u32 cur_hold_line;
#ifdef CONFIG_AMLOGIC_VPU
struct vpu_dev_s *arb_vpu_dev;
#endif
int i;
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
void *video_secure_op[VPP_TOP_MAX] = {VSYNC_WR_MPEG_REG_BITS,
VSYNC_WR_MPEG_REG_BITS_VPP1,
VSYNC_WR_MPEG_REG_BITS_VPP2,
PRE_VSYNC_WR_MPEG_REG_BITS};
#endif
_video_hw_init();
/* temp: enable VPU arb mem */
#ifdef CONFIG_AMLOGIC_VPU
vd1_vpu_dev = vpu_dev_register(VPU_VIU_VD1, "VD1");
@@ -13547,12 +13632,7 @@ int video_hw_init(void)
arb_vpu_dev = vpu_dev_register(VPU_VPU_ARB, "ARB");
vpu_dev_mem_power_on(arb_vpu_dev);
#endif
/*disable sr default when power up*/
WRITE_VCBUS_REG(VPP_SRSHARP0_CTRL, 0);
WRITE_VCBUS_REG(VPP_SRSHARP1_CTRL, 0);
/* disable aisr_sr1_nn func */
if (cur_dev->aisr_support)
aisr_sr1_nn_enable(0);
if (cur_dev->display_module != C3_DISPLAY_MODULE) {
cur_hold_line = READ_VCBUS_REG(VPP_HOLD_LINES + cur_dev->vpp_off);
cur_hold_line = cur_hold_line & 0xff;
@@ -13564,80 +13644,14 @@ int video_hw_init(void)
else
vpp_hold_line[0] = cur_hold_line;
/* Temp force set dmc */
if (!legacy_vpp) {
if (cur_dev->display_module == OLD_DISPLAY_MODULE ||
video_is_meson_t5w_cpu())
WRITE_DMCREG
(DMC_AM0_CHAN_CTRL,
0x8ff403cf);
if (video_is_meson_t5m_cpu())
WRITE_VCBUS_REG(VPU_RDARB_UGT_L2C1, 0xffff);
/* for vd1 & vd2 dummy alpha*/
WRITE_VCBUS_REG
(VPP_POST_BLEND_DUMMY_ALPHA,
0x7fffffff);
WRITE_VCBUS_REG_BITS
(VPP_MISC1, 0x100, 0, 9);
}
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
/* disable latch for sr core0/1 scaler */
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 0, 1);
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 8, 1);
WRITE_VCBUS_REG_BITS
(sr_info.sr1_sharp_sync_ctrl,
1, 8, 1);
if (cur_dev->aisr_support)
WRITE_VCBUS_REG_BITS
(sr_info.sr1_sharp_sync_ctrl,
1, 17, 1);
} else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12B)) {
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 0, 1);
WRITE_VCBUS_REG_BITS
(sr_info.sr0_sharp_sync_ctrl,
1, 8, 1);
}
/* force bypass dolby for TL1/T5, no dolby function */
if (!glayer_info[0].dv_support && !is_meson_s4d_cpu())
WRITE_VCBUS_REG_BITS(AMDV_PATH_CTRL, 0xf, 0, 6);
for (i = 0; i < MAX_VD_LAYER; i++) {
if (glayer_info[i].fgrain_support)
fgrain_init(i, FGRAIN_TBL_SIZE);
}
if (video_is_meson_t7_cpu()) {
/* vpu port map for t7 */
/* vpp_arb0: osd1, vd1, osd3, dolby0, vd3 */
/* vpp_arb1: osd2, vd2, osd4, mali-afbc */
/* arb rd0: vpp_arb0, rdma read, ldim, vdin_afbce, vpu dma */
/* arb rd2: vpp_arb1, */
/* VPU[0x3978]=0x0aa00000 */
/* VPU[0x279d]=0x00900000 */
/*
*setting move to vpu arb driver init
*WRITE_VCBUS_REG(VPU_RDARB_UGT_L2C1, 0xffff);
*/
} else if (video_is_meson_t5m_cpu()) {
/* vpu port map for t5m */
/* vpp_arb0: vd1, vd2, dolby0 */
/* vpp_arb1: osd1, osd2, osd3, mali-afbc */
/* arb rd0: vpp_arb0, rdma read, vpu sub, dcntr, tcon p2 */
/* arb rd2: vpp_arb1, tcon p1 */
/* VPU[0x3978]=0x0b300000 */
/* VPU[0x279d]=0x00920000 */
/* vpp_arb0, vpp_arb1 super urgent */
WRITE_VCBUS_REG(VPU_RDARB_UGT_L2C1, 0xffff);
}
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
secure_register(VIDEO_MODULE, 0, video_secure_op, vpp_secure_cb);
#endif
vd_set_go_field_default();
return 0;
}
@@ -14069,6 +14083,20 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo)
return r;
}
void video_resume_hw_recovery(void)
{
if (cur_dev->display_module == S5_DISPLAY_MODULE)
_video_hw_init_s5();
else
_video_hw_init();
vpp_probe_en_set(1);
vd_layer[0].property_changed = true;
vd_layer[1].property_changed = true;
vd_layer[2].property_changed = true;
vd_layer_vpp[0].property_changed = true;
vd_layer_vpp[1].property_changed = true;
}
int video_late_uninit(void)
{
int i;
drivers/media/video_sink/video_hw_s5.c
+15 -7
View File
@@ -12624,7 +12624,7 @@ static void save_vd_pps_reg(void)
}
}
int video_hw_init_s5(void)
int _video_hw_init_s5(void)
{
struct vd_proc_misc_reg_s *vd_proc_misc_reg = NULL;
struct vpp_post_blend_reg_s *vpp_post_blend_reg = NULL;
@@ -12639,12 +12639,6 @@ int video_hw_init_s5(void)
vd_proc_blend_reg = &vd_proc_reg.vd_proc_blend_reg;
vd2_pre_blend_reg = &vd_proc_reg.vd2_pre_blend_reg;
vd_proc_sr_reg = &vd_proc_reg.vd_proc_sr_reg;
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
void *video_secure_op[VPP_TOP_MAX] = {VSYNC_WR_MPEG_REG_BITS,
VSYNC_WR_MPEG_REG_BITS_VPP1,
VSYNC_WR_MPEG_REG_BITS_VPP2,
PRE_VSYNC_WR_MPEG_REG_BITS};
#endif
WRITE_VCBUS_REG_BITS
(vpp_post_misc_reg->vpp_ofifo_size,
@@ -12742,6 +12736,20 @@ int video_hw_init_s5(void)
WRITE_VCBUS_REG(VPU_AXI_QOS_WR0, 0xfb73fedc);
}
save_vd_pps_reg();
return 0;
}
int video_hw_init_s5(void)
{
#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
void *video_secure_op[VPP_TOP_MAX] = {VSYNC_WR_MPEG_REG_BITS,
VSYNC_WR_MPEG_REG_BITS_VPP1,
VSYNC_WR_MPEG_REG_BITS_VPP2,
PRE_VSYNC_WR_MPEG_REG_BITS};
#endif
_video_hw_init_s5();
#ifdef CONFIG_AMLOGIC_MEDIA_LUT_DMA
int i;
drivers/media/video_sink/video_priv.h
+2
View File
@@ -869,6 +869,7 @@ int video_early_init(struct amvideo_device_data_s *p_amvideo);
int video_late_uninit(void);
int video_hw_init_s5(void);
int _video_hw_init_s5(void);
int video_early_init_s5(struct amvideo_device_data_s *p_amvideo);
void vd_scaler_setting_s5(struct video_layer_s *layer,
struct scaler_setting_s *setting);
@@ -900,6 +901,7 @@ struct mosaic_frame_s *get_mosaic_vframe_info(u32 slice);
void get_mosaic_axis(void);
void set_mosaic_axis(u32 pic_index, u32 x_start, u32 y_start,
u32 x_end, u32 y_end);
void video_resume_hw_recovery(void);
/* from video.c */
extern u32 osd_vpp_misc;