shinys000114/kernel_common_drivers
1
0
Fork 0
mirror of https://github.com/hardkernel/kernel_common_drivers.git synced 2026-06-25 12:03:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

hdmirx: fix trim value is changed when rx probe [1/1]

Browse Source 
PD#SWPL-141485

Problem:
trim value is changed when rx probe.

Solution:
add trim flow.

Verify:
txhd2

Change-Id: I27e3bf109e6898100e4d780be8441258943edca3
Signed-off-by: yaoyu.xu <yaoyu.xu@amlogic.com>
This commit is contained in:
yaoyu.xu
2023-09-28 13:23:46 +08:00
committed by Luan Yuan
parent 70261aa779
commit e671fc5f00
2 changed files with 10 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+2 -1
View File
@@ -107,7 +107,8 @@
/* 2023.08.28 support FRL 3G3L & 6G3L */
/* 2023.08.31 add vpp mute cnt */
/* 2023.9.14 add support for 240p */
#define RX_VER1 "ver.2023/9/14"
/* 2023 09.28 add trim flow for txhd2 */
#define RX_VER1 "ver.2023/9/28"
/* 50ms timer for hdmirx main loop (HDMI_STATE_CHECK_FREQ is 20) */
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_txhd2.c
+8 -1
View File
@@ -631,6 +631,8 @@ void aml_dfe_en_txhd2(void)
void aml_phy_offset_cal_txhd2(void)
{
/* PHY */
u32 data32;
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHD_EQ, 0x70080050);
usleep_range(10, 20);
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHD_CDR, 0x04008013);
@@ -641,7 +643,12 @@ void aml_phy_offset_cal_txhd2(void)
usleep_range(10, 20);
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC2, 0x11c73220);
usleep_range(10, 20);
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC1, 0xffe00100);
data32 = 0xffe00100;
if (rterm_trim_flag_txhd2) {
data32 = ((data32 & (~((0xf << 12) | 0x1))) |
(rterm_trim_val_txhd2 << 12) | rterm_trim_flag_txhd2);
}
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC1, data32);
usleep_range(10, 20);
/* PLL */