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hdmirx: Fix t3x bright line issue on frl mode [1/1]

Browse Source 
PD#SWPL-141904

Problem:
t3x flash bright lines when switching colorspace

Solution:
Perform a core reset when the bright line flashes

Verify:
t3x

Change-Id: I4cbe1cb5bea9b8b3c85b103170c1f78530daa694
Signed-off-by: Gaowei Zhao <gaowei.zhao@amlogic.com>
This commit is contained in:
Gaowei Zhao
2023-11-20 11:16:15 +08:00
committed by Luan Yuan
parent 329755c9d1
commit e8493df940
4 changed files with 56 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+2
View File
@@ -5315,6 +5315,8 @@ void hdmirx_config_video(u8 port)
set_dv_ll_mode(false, port);
hdmirx_output_en(true);
rx_irq_en(true, port);
if (rx[port].var.frl_rate)
cor_debug_t3x(port);
hdmirx_top_irq_en(1, 2, port);
if (rx_info.chip_id < CHIP_ID_T7)
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.c
+20
View File
@@ -5923,3 +5923,23 @@ void rx_cor_reset_t3x(u8 port)
hdmirx_wr_top(TOP_SW_RESET, 0, port);
}
void clr_frl_fifo_status(u8 port)
{
hdmirx_wr_cor(VP_FDET_IRQ_STATUS_VID_IVCRX, 0xff, port);
udelay(1);
hdmirx_wr_cor(VP_FDET_IRQ_STATUS_VID_IVCRX + 1, 0xff, port);
udelay(1);
hdmirx_wr_cor(VP_FDET_IRQ_STATUS_VID_IVCRX + 2, 0xff, port);
}
void cor_debug_t3x(u8 port)
{
hdmirx_wr_cor(VP_FDET_IRQ_MASK_VID_IVCRX, 0x80, port);
udelay(1);
hdmirx_wr_cor(VP_FDET_IRQ_MASK_VID_IVCRX + 1, 0x7, port);
udelay(1);
hdmirx_wr_cor(VP_FDET_IRQ_MASK_VID_IVCRX + 2, 0x0, port);
udelay(1);
hdmirx_wr_bits_cor(RX_GRP_INTR1_MASK_PWD_IVCRX, _BIT(1), 1, port);
}
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t3x.h
+2
View File
@@ -220,6 +220,8 @@ void aml_phy_power_off_t3x_port1(void);
void aml_phy_power_off_t3x_port2(void);
void aml_phy_power_off_t3x_port3(void);
void rx_cor_reset_t3x(u8 port);
void cor_debug_t3x(u8 port);
void clr_frl_fifo_status(u8 port);
//void reset_pcs(void);
drivers/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
+32
View File
@@ -75,6 +75,7 @@ static int wait_no_sig_max = 600;
static int fpll_stable_max = 50;
u32 vrr_func_en = 1;
u32 allm_func_en = 0xff;
u32 htotal_cnt;
typedef void (*pf_callback)(int earc_port, bool st);
static pf_callback earc_hdmirx_hpdst;
@@ -2257,6 +2258,7 @@ irqreturn_t irq2_handler(int irq, void *params)
int error = 0;
bool emp_rcvd;
u32 tmp = 0;
int status = 0;
if (params == 0) {
rx_pr("%s: %s\n", __func__,
@@ -2394,6 +2396,18 @@ irqreturn_t irq2_handler(int irq, void *params)
rx_pr("overlap!!! 0x152f:0x%x, 0x1563:0x%x\n", tmp,
hdmirx_rd_cor(H21RXSB_INTR3_M42H_IVCRX, E_PORT2));
}
if (rx[E_PORT2].var.frl_rate && rx[E_PORT2].state >= FSM_SIG_STABLE) {
status = hdmirx_rd_bits_cor(VP_FDET_IRQ_STATUS_VID_IVCRX,
MSK(4, 7), E_PORT2);
if (status != 0) {
clr_frl_fifo_status(E_PORT2);
htotal_cnt++;
if (htotal_cnt >= 10) {
rx_cor_reset_t3x(E_PORT2);
htotal_cnt = 0;
}
}
}
}
if (hdmirx_top_intr_stat & (1 << 0))
if (log_level & COR_LOG)
@@ -2410,6 +2424,7 @@ irqreturn_t irq3_handler(int irq, void *params)
int error = 0;
bool emp_rcvd;
u32 tmp = 0;
int status = 0;
if (params == 0) {
rx_pr("%s: %s\n", __func__,
@@ -2547,6 +2562,19 @@ irqreturn_t irq3_handler(int irq, void *params)
rx_pr("overlap!!! 0x152f:0x%x, 0x1563:0x%x\n", tmp,
hdmirx_rd_cor(H21RXSB_INTR3_M42H_IVCRX, E_PORT3));
}
if (rx[E_PORT3].var.frl_rate && rx[E_PORT3].state >= FSM_SIG_STABLE) {
status = hdmirx_rd_bits_cor(VP_FDET_IRQ_STATUS_VID_IVCRX,
MSK(4, 7), E_PORT3);
if (status != 0) {
clr_frl_fifo_status(E_PORT3);
htotal_cnt++;
if (htotal_cnt >= 10) {
if (rx[E_PORT3].var.dbg_ve)
rx_cor_reset_t3x(E_PORT3);
htotal_cnt = 0;
}
}
}
}
if (hdmirx_top_intr_stat & (1 << 0))
if (log_level & COR_LOG)
@@ -6581,6 +6609,8 @@ void rx_port2_main_state_machine(void)
}
rx[port].state = FSM_SIG_UNSTABLE;
rx[port].var.clk_stable_cnt = 0;
htotal_cnt = 0;
clr_frl_fifo_status(port);
break;
case FSM_WAIT_CLK_STABLE:
if (rx[port].cur_5v_sts == 0)
@@ -7135,6 +7165,8 @@ void rx_port3_main_state_machine(void)
}
rx[port].state = FSM_SIG_UNSTABLE;
rx[port].var.clk_stable_cnt = 0;
htotal_cnt = 0;
clr_frl_fifo_status(port);
break;
case FSM_WAIT_CLK_STABLE:
if (rx[port].cur_5v_sts == 0)