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drm: Display black screen 10s beteween logo and Startup video [1/1]

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PD#SWPL-142765

Problem:
1.Because the first display skipped updating the register,
the scope obtained by vpp from postblend is incorrect.
2.The address of the logo is located at the front end of mem

Solution:
1.Read scope reg in postblend_init and return to vpp
2.Move the address of the logo back

Verify:
t3x

Test:
DRM-OSD-117

Change-Id: I6acc1464f24cc6326f509a0decdc280a612cac40
Signed-off-by: congyang.huang <congyang.huang@amlogic.com>
This commit is contained in:
congyang.huang
2023-10-20 18:33:09 +08:00
committed by gerrit autosubmit
parent 0e45509260
commit ed2efb2df8
2 changed files with 21 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/t3x_t968d4_bc302.dts
+4 -5
View File
@@ -108,11 +108,10 @@
/*};*/
logo_reserved:linux,meson-fb {
compatible = "shared-dma-pool";
reusable;
compatible = "amlogic, meson-fb";
size = <0x0 0x800000>;
alignment = <0x0 0x400000>;
reg = <0x0 0x3e800000 0x0 0x800000>;
reg = <0x0 0xdf800000 0x0 0x800000>;
};
lcd_tcon_reserved:linux,lcd_tcon {
@@ -1883,14 +1882,14 @@
display_size_default = <3840 2160 3840 4320 32>;
mem_size = <0x00800000 0x4000000 0x100000>;
4k2k_fb = <1>;
logo_addr = "0x3e800000";
logo_addr = "0xdf800000";
mem_alloc = <0>;
pxp_mode = <0>; /** 0:normal mode 1:pxp mode */
};
&drm_vpu {
status = "okay";
logo_addr = "0x3e800000";
logo_addr = "0xdf800000";
connectors_dev: port@1 {
drm_to_lcd0: endpoint@0 {
drivers/drm/vpu-hw/meson_vpu_postblend.c
+17
View File
@@ -23,6 +23,7 @@
#include "meson_vpu_util.h"
#include "meson_vpu_reg.h"
#include "meson_vpu_postblend.h"
#include "meson_osd_proc.h"
static u32 osd_vpp_misc_mask = 0x33330;
static u32 osd_vpp1_bld_ctrl;
@@ -1116,7 +1117,23 @@ static void s5_postblend_hw_init(struct meson_vpu_block *vblk)
static void t3x_postblend_hw_init(struct meson_vpu_block *vblk)
{
int reg_h = 0, reg_v = 0;
struct meson_vpu_postblend *postblend = to_postblend_block(vblk);
struct meson_vpu_pipeline *pipeline = postblend->base.pipeline;
struct meson_vpu_sub_pipeline_state *mvsps;
struct meson_vpu_pipeline_state *mvps;
s5_postblend_hw_init(vblk);
mvps = priv_to_pipeline_state(pipeline->obj.state);
mvsps = &mvps->sub_states[0];
reg_h = meson_drm_read_reg(postblend->reg->vpp_osd1_bld_h_scope);
reg_v = meson_drm_read_reg(postblend->reg->vpp_osd1_bld_v_scope);
vpp_osd1_scope.h_start = (reg_h & 0xffff0000) >> 16;
vpp_osd1_scope.v_start = (reg_v & 0xffff0000) >> 16;
vpp_osd1_scope.h_end = reg_h & 0xffff;
vpp_osd1_scope.v_end = reg_v & 0xffff;
#ifdef CONFIG_AMLOGIC_MEDIA_VIDEO
register_vpp_postblend_info_func(get_postblend_osd1_scope);
#endif