vpu_security: correct abnormal VPU security values after enabling prevsync [1/1]

PD#SWPL-187270

Problem:
encrypted video displays abnormally

Solution:
correct the security values

Verify:
t5m

Change-Id: Id64275e58d1f1023b71f3a13abfad37c7d73c4df
Signed-off-by: Jian Cao <jian.cao@amlogic.com>
This commit is contained in:
Jian Cao
2024-09-29 07:45:19 +00:00
committed by gerrit autosubmit
parent 20c713319c
commit f3b506a2d6
2 changed files with 12 additions and 3 deletions
@@ -350,10 +350,19 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
struct vd_secure_info_s vd_secure[MAX_SECURE_OUT];
bool vpp_top_en = 0;
struct vpu_sec_bit_s change;
u32 reg_vpp_index = vpp_index;
version = vpu_secure_version();
if (!is_vpu_secure_support())
return 0;
/* prevsync belongs to the screen corresponding to VPP_TOP,
* but when updating the register, the RDMA channel of prevsync needs to be used.
* Therefore, there are two variables: vpp_index and reg_vpp_index.
*/
if (vpp_index == VPP_PRE_VSYNC)
vpp_index = VPP_TOP;
switch (module) {
case OSD_MODULE:
if ((secure_src & OSD1_INPUT_SECURE) ||
@@ -486,7 +495,7 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
pr_info("line=%d,module=%d value=0x%x, value_save=0x%x, bit_changed=0x%x\n",
__LINE__, module, value, value_save[vpp_index],
change.bit_changed);
secure_reg_update(ins, &change, vpp_index);
secure_reg_update(ins, &change, reg_vpp_index);
secure_update = 1;
}
value_save[vpp_index] = value;
+2 -2
View File
@@ -13868,7 +13868,7 @@ void video_secure_set(u8 vpp_index)
layer = get_layer_by_layer_id(i);
/* layer is NULL or vpp_index does not match, skip */
if (!layer || layer->vpp_index != vpp_index)
if (!layer/* || layer->vpp_index != vpp_index*/)
continue;
if (layer->dispbuf &&
(layer->dispbuf->flag & VFRAME_FLAG_VIDEO_SECURE))
@@ -13898,7 +13898,7 @@ void video_secure_set(u8 vpp_index)
else if (layer->layer_id == 1)
secure_src |= VD2_FGRAIN_SECURE;
}
video_enable |= layer->enabled;
video_enable |= layer->enabled << i;
}
if (video_enable) {