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dsc: add get dsc pix_per_clk [1/1]

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PD#SWPL-142209

Problem:
vdin not get dsc pix_per_clk

Solution:
add get dsc pix_per_clk

Verify:
t3x

Change-Id: I4371ff1173f0e3cb53e9dea1ed127d1fcb597868
Signed-off-by: qiang.liu <qiang.liu@amlogic.com>
This commit is contained in:
qiang.liu
2023-10-10 19:52:14 +08:00
committed by gerrit autosubmit
parent bfa2c539df
commit f54f40e14b
10 changed files with 48 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vin/tvin/dsc_dec/dsc_dec_config.c
+25 -20
View File
@@ -202,10 +202,11 @@ void init_pps_data_4k_120hz(struct aml_dsc_dec_drv_s *dsc_dec_drv)
dsc_dec_drv->tmg_ctrl.tmg_vso_eline = 13;
dsc_dec_drv->tmg_cb_von_bline = 85;
dsc_dec_drv->tmg_cb_von_eline = 2245;
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
if (dsc_dec_drv->dsc_dec_en) {
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
}
}
//config 4k60hz rgb 8bpc 12bpp
@@ -368,10 +369,11 @@ void init_pps_data_4k_60hz(struct aml_dsc_dec_drv_s *dsc_dec_drv)
dsc_dec_drv->tmg_ctrl.tmg_vso_eline = 13;
dsc_dec_drv->tmg_cb_von_bline = 85;
dsc_dec_drv->tmg_cb_von_eline = 2245;
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
if (dsc_dec_drv->dsc_dec_en) {
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
}
}
//config 8k30hz rgb 8bpc 12bpp
@@ -534,10 +536,11 @@ void init_pps_data_8k_30hz(struct aml_dsc_dec_drv_s *dsc_dec_drv)
dsc_dec_drv->tmg_ctrl.tmg_vso_eline = 22;
dsc_dec_drv->tmg_cb_von_bline = 65;
dsc_dec_drv->tmg_cb_von_eline = 4385;
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
if (dsc_dec_drv->dsc_dec_en) {
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
}
}
//config 8k60hz rgb 8bpc 9.9375bpp
@@ -701,10 +704,11 @@ void init_pps_data_8k_60hz_8bpc(struct aml_dsc_dec_drv_s *dsc_dec_drv)
dsc_dec_drv->tmg_ctrl.tmg_vso_eline = 22;
dsc_dec_drv->tmg_cb_von_bline = 65;
dsc_dec_drv->tmg_cb_von_eline = 4385;
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
if (dsc_dec_drv->dsc_dec_en) {
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
}
}
//config 8k60hz YUV444 10bpc 9.9375bpp
@@ -868,10 +872,11 @@ void init_pps_data_8k_60hz_10bpc(struct aml_dsc_dec_drv_s *dsc_dec_drv)
dsc_dec_drv->tmg_ctrl.tmg_vso_eline = 22;
dsc_dec_drv->tmg_cb_von_bline = 65;
dsc_dec_drv->tmg_cb_von_eline = 4385;
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
if (dsc_dec_drv->dsc_dec_en) {
dsc_dec_config_register(dsc_dec_drv);
dsc_dec_config_vpu_mux(dsc_dec_drv);
set_dsc_dec_en(1);
}
}
/* integer: clk integer (M)
drivers/media/vin/tvin/dsc_dec/dsc_dec_debug.c
+2 -2
View File
@@ -555,8 +555,8 @@ static ssize_t dsc_dec_debug_store(struct device *dev,
init_pps_data_8k_60hz_10bpc(dsc_dec_drv);
} else if (!strcmp(parm[0], "is_enable_dsc_dec")) {
if (parm[1] && (kstrtouint(parm[1], 10, &temp) == 0))
set_dsc_dec_en(temp);
DSC_DEC_PR("is_enable_dsc value:%d\n", temp);
dsc_dec_drv->dsc_dec_en = temp;
DSC_DEC_PR("is_enable_dsc value:%d\n", dsc_dec_drv->dsc_dec_en);
} else if (!strcmp(parm[0], "manual_dsc_tmg")) {
set_dsc_tmg_ctrl(dsc_dec_drv, (char **)&parm);
} else if (!strcmp(parm[0], "clr_dsc_dec_status")) {
drivers/media/vin/tvin/dsc_dec/dsc_dec_drv.c
+2 -2
View File
@@ -240,8 +240,8 @@ static int dsc_dec_probe(struct platform_device *pdev)
dsc_dec_debug_file_create(dsc_dec_drv);
dsc_dec_ioremap(pdev, dsc_dec_drv);
init_pps_data_4k_120hz(dsc_dec_drv);
DSC_DEC_PR("%s ok, init_state\n", __func__);
set_dsc_dec_en(0);
DSC_DEC_PR("%s, driver initialized ok\n", __func__);
return 0;
}
drivers/media/vin/tvin/dsc_dec/dsc_dec_drv.h
+1 -1
View File
@@ -62,7 +62,7 @@ struct aml_dsc_dec_drv_s {
unsigned int slice_num_m1;//pic_width/slice_width;
unsigned int dsc_dec_en;
unsigned int dsc_dec_frm_latch_en;// need to check ucode
unsigned int pix_per_clk;//input 0:1pix 1:2pix 2:4pix
u8 pix_per_clk;//input 0:1pix 1:2pix 2:4pix
bool c3_clk_en;
bool c2_clk_en;
bool c1_clk_en;
drivers/media/vin/tvin/dsc_dec/dsc_dec_hw.c
+2 -1
View File
@@ -80,9 +80,11 @@ void set_dsc_dec_en(unsigned int enable)
if (enable) {
W_DSC_DEC_BIT(DSC_ASIC_CTRL0, 1, DSC_DEC_EN, DSC_DEC_EN_WID);
W_DSC_DEC_BIT(DSC_ASIC_CTRL3, 1, TMG_EN, TMG_EN_WID);
W_DSC_DEC_CLKCTRL_REG(CLKCTRL_DSC_CLK_CTRL, 0x1c0);
} else {
W_DSC_DEC_BIT(DSC_ASIC_CTRL0, 0, DSC_DEC_EN, DSC_DEC_EN_WID);
W_DSC_DEC_BIT(DSC_ASIC_CTRL3, 0, TMG_EN, TMG_EN_WID);
W_DSC_DEC_CLKCTRL_REG(CLKCTRL_DSC_CLK_CTRL, 0x2c0);
}
}
@@ -322,7 +324,6 @@ void dsc_dec_config_fix_pll_clk(unsigned int value)
usleep_range(20, 30);
W_DSC_DEC_CLKCTRL_REG(CLKCTRL_PIX_PLL_CTRL3, 0x090da200);
}
W_DSC_DEC_CLKCTRL_REG(CLKCTRL_DSC_CLK_CTRL, 0x1c0);
}
void dsc_dec_config_pll_clk(unsigned int od, unsigned int dpll_m,
drivers/media/vin/tvin/dsc_dec/dsc_dec_reg.h
+3
View File
@@ -8,6 +8,9 @@
//pll clk register
#define CLKCTRL_DSC_CLK_CTRL 0x0040
// BIT 6 gate = 1
// BIT 16 N = 0 : cts_dsc_pix_clk_sel
// BIT 7:9 = 3:dsc_pix_pll 5:hifi1
#define CLKCTRL_PIX_PLL_CTRL0 0x02f0
#define CLKCTRL_PIX_PLL_CTRL1 0x02f1
#define CLKCTRL_PIX_PLL_CTRL2 0x02f2
drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+10
View File
@@ -1570,6 +1570,15 @@ void hdmirx_get_avi_ext_colorimetry(struct tvin_sig_property_s *prop, u8 port)
}
}
/* frl is 2ppc or 4ppc; tmds is 1ppc (420+2ppc;420+4ppc up_sample_en need enable to 1) */
void hdmirx_get_up_sample_en(struct tvin_sig_property_s *prop, u8 port)
{
if (rx[port].var.frl_rate && rx[port].cur.colorspace == E_COLOR_YUV420)
prop->up_sample_en = 1;
else
prop->up_sample_en = 0;
}
/***************************************************
*func: hdmirx_get_sig_property - get signal property
**************************************************/
@@ -1595,6 +1604,7 @@ void hdmirx_get_sig_prop(struct tvin_frontend_s *fe,
hdmirx_get_hdcp_sts(prop, rx_info.main_port);
hdmirx_get_hw_vic(prop, rx_info.main_port);
hdmirx_get_avi_ext_colorimetry(prop, rx_info.main_port);
hdmirx_get_up_sample_en(prop, rx_info.main_port);
prop->skip_vf_num = vdin_drop_frame_cnt;
if (log_level & SIG_PROP_LOG) {
rx_pr("dvi:%#x,color[%d,%#x,%#x,%#x],fps:%d,spd[%#x,%#x]\n",
drivers/media/vin/tvin/tvin_global.h
+1
View File
@@ -569,6 +569,7 @@ struct tvin_sig_property_s {
struct tvin_3d_meta_data_s threed_info;
u8 dolby_vision;/*is signal dolby version 1:vsif 2:emp */
bool low_latency;/*is low latency dolby mode*/
u8 up_sample_en;/* 420+2ppc 420+4ppc need enable to 1 */
u8 fps;
unsigned int skip_vf_num;/*skip pre vframe num*/
struct tvin_latency_s latency;
drivers/media/vin/tvin/vdin/vdin_ctl_t3x.c
+1 -19
View File
@@ -527,11 +527,9 @@ void vdin_set_top_t3x(struct vdin_dev_s *devp, enum tvin_port_e port,
unsigned int offset = devp->addr_offset;
unsigned int vdin_mux = VDIN_MUX_NULL;
unsigned int vdi_size = 0;
unsigned int value = 0;
unsigned int vdin_data_bus_0 = VDIN_MAP_Y_G;
unsigned int vdin_data_bus_1 = VDIN_MAP_BPB;
unsigned int vdin_data_bus_2 = VDIN_MAP_RCR;
void __iomem *dsc_clk;
pr_info("%s %d:port:%#x,input_cfmt:%d\n",
__func__, __LINE__, port, input_cfmt);
@@ -573,19 +571,6 @@ void vdin_set_top_t3x(struct vdin_dev_s *devp, enum tvin_port_e port,
vdin_mux = VDIN_VDI4A_HDMIRX_T3X;
wr(0, VDIN_INTF_VDI4A_CTRL, 0xe4);
wr(0, VDIN_INTF_VDI4A_SIZE, vdi_size);
/* Move DSC clock setting to DSC decoder in the future */
//bit6=1,bit16=0;non-dsc bit7:9 = 5;dsc = 3
//value = codecio_read_nocbus(DSC_CLK_CTRL_OFFSET);
dsc_clk = ioremap(CLKCTRL_DSC_CLK_CTRL, sizeof(CLKCTRL_DSC_CLK_CTRL));
value = readl(dsc_clk);
value |= (1 << 6);
value &= ~(1 << 16);
value &= ~(7 << 7);
value |= (5 << 7);
writel(value, dsc_clk);
iounmap(dsc_clk);
//codecio_write_nocbus(DSC_CLK_CTRL_OFFSET, value);
pr_info("%s %d:value:%#x\n", __func__, __LINE__, value);
// }
vdin_data_bus_0 = VDIN_MAP_RCR;
vdin_data_bus_1 = VDIN_MAP_Y_G;
@@ -697,10 +682,7 @@ void vdin_set_top_t3x(struct vdin_dev_s *devp, enum tvin_port_e port,
wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 1, 4, 2); /* reg_hskip_mode */
if (devp->v_skip_en)
wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 1, 7, 1); /* reg_vskip_en */
if (input_cfmt == TVIN_YUV420)
wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 1, 30, 1);
else
wr_bits(0, VPU_VDIN_HDMI0_CTRL1, 0, 30, 1);
wr_bits(0, VPU_VDIN_HDMI0_CTRL1, devp->pre_prop.up_sample_en, 30, 1);
}
/*this function will set the bellow parameters of devp:
drivers/media/vin/tvin/vdin/vdin_regs_t3x.h
+1 -1
View File
@@ -60,7 +60,7 @@ enum vdin_vdi_x_t3x_e {
// Bit 27:16 reg_rdwin_manual
// Bit 28 reg_dbv422_mode
// Bit 29 reg_afifo_rate
// Bit 30 reg_upsmp_en : 0:disable 1: 4ppc to 2ppc (not skip)
// Bit 30 reg_upsmp_en:0:disable 1:4ppc to 2ppc(not skip) (420+2ppc or 420+4ppc need 1)
// bit 31 disable_rst_afifo
#define VPU_VDIN_HDMI1_CTRL0 0x272e
// Bit 27:24 reg_yuv_swap