drm: add osd security support [1/1]

PD#SWPL-107108

Problem:
T5M VPU has security feature

Solution:
add osd security feature

Verify:
t5m

Test:
gpu sftest

Change-Id: I0075d7aeaf525fc14f6703f127f7dc17e6fc19ae
Signed-off-by: congyang.huang <congyang.huang@amlogic.com>

drivers/drm/meson_plane.c

@@ -595,11 +595,17 @@ static int meson_plane_atomic_get_property(struct drm_plane *plane,
 					uint64_t *val)
 {
 	struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
+	struct am_meson_plane_state *plane_state;
 	int ret = 0;
 
+	plane_state = to_am_meson_plane_state(state);
+
 	if (property == osd_plane->occupied_property) {
 		*val = osd_plane->osd_occupied;
 		return 0;
+	} else if (property == osd_plane->prop_sec_en) {
+		*val = plane_state->sec_en;
+		ret = 0;
 	}
 
 	return ret;
@@ -611,11 +617,17 @@ static int meson_plane_atomic_set_property(struct drm_plane *plane,
 					 uint64_t val)
 {
 	struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
+	struct am_meson_plane_state *plane_state;
 	int ret = 0;
 
+	plane_state = to_am_meson_plane_state(state);
+
 	if (property == osd_plane->occupied_property) {
 		osd_plane->osd_occupied = val;
 		return 0;
+	} else if (property == osd_plane->prop_sec_en) {
+		plane_state->sec_en = val;
+		ret = 0;
 	}
 
 	return ret;
@@ -974,6 +986,7 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
 	struct am_osd_plane *osd_plane = to_am_osd_plane(plane);
 	struct meson_drm *drv = osd_plane->drv;
 	struct drm_plane_state *state;
+	struct am_meson_plane_state *plane_state;
 	int ret;
 
 	state = drm_atomic_get_new_plane_state(atomic_state, plane);
@@ -1037,6 +1050,9 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
 	if (state->crtc)
 		plane_info->crtc_index = state->crtc->index;
 
+	plane_state = to_am_meson_plane_state(state);
+	plane_info->sec_en = plane_state->sec_en;
+
 	DRM_DEBUG("OSD PLANE index=%d, zorder=%d, premult= %d, alpha = %d, phy = %llx\n",
 		  plane_info->plane_index, plane_info->zorder,
 		  state->pixel_blend_mode, plane_info->global_alpha,
@@ -1277,6 +1293,20 @@ static const struct drm_plane_helper_funcs am_video_helper_funcs = {
 	.atomic_async_update = meson_osd_plane_async_update,
 };
 
+static void meson_plane_create_security_en_property(struct drm_device *drm_dev,
+						  struct am_osd_plane *osd_plane)
+{
+	struct drm_property *prop;
+
+	prop = drm_property_create_bool(drm_dev, 0, "SEC_EN");
+	if (prop) {
+		osd_plane->prop_sec_en = prop;
+		drm_object_attach_property(&osd_plane->base.base, prop, 0);
+	} else {
+		DRM_ERROR("Failed to SEC_EN property\n");
+	}
+}
+
 struct drm_property *
 meson_create_scaling_filter_prop(struct drm_device *dev,
 			       unsigned int supported_filters)
@@ -1491,6 +1521,7 @@ static struct am_osd_plane *am_osd_plane_create(struct meson_drm *priv,
 	meson_plane_add_occupied_property(priv->drm, osd_plane);
 	DRM_INFO("osd plane %d create done, occupied-%d crtcmask-%d type-%d\n",
 		i, osd_plane->osd_occupied, crtc_mask, type);
+	meson_plane_create_security_en_property(priv->drm, osd_plane);
 	return osd_plane;
 }
 

drivers/drm/meson_plane.h

@@ -22,6 +22,7 @@
 
 struct am_meson_plane_state {
 	struct drm_plane_state base;
+	u32 sec_en;
 };
 
 enum meson_plane_type {
@@ -38,6 +39,7 @@ struct am_osd_plane {
 	int plane_type;
 
 	struct drm_property *occupied_property;
+	struct drm_property *prop_sec_en;
 	bool osd_occupied;
 
 	/*osd extend*/

drivers/drm/meson_vpu_pipeline.h

@@ -180,6 +180,7 @@ struct meson_vpu_osd_layer_info {
 	u32 crtc_index;
 	u32 read_ports;
 	u32 status_changed;
+	int sec_en;
 };
 
 struct meson_vpu_osd {
@@ -222,6 +223,7 @@ struct meson_vpu_osd_state {
 	u32 blend_bypass;
 	u32 crtc_index;
 	u32 read_ports;
+	int sec_en;
 };
 
 struct meson_vpu_video_layer_info {
@@ -247,6 +249,7 @@ struct meson_vpu_video_layer_info {
 	struct dma_buf *dmabuf;
 	u32 vfm_mode;
 	bool is_uvm;
+	int sec_en;
 };
 
 struct meson_vpu_video {
@@ -300,6 +303,7 @@ struct meson_vpu_video_state {
 	struct vframe_s *vf;
 	struct dma_buf *dmabuf;
 	bool is_uvm;
+	int sec_en;
 };
 
 struct meson_vpu_afbc {
@@ -524,6 +528,7 @@ struct meson_vpu_pipeline_state {
 	struct meson_vpu_block *scale_blk[MESON_MAX_OSDS][MESON_MAX_SCALERS];
 	u32 dout_zorder[MAX_DOUT_NUM];
 	u32 global_afbc;
+	int sec_src;
 };
 
 #define to_osd_block(x) container_of(x, struct meson_vpu_osd, base)

drivers/drm/meson_vpu_util.c

@@ -164,7 +164,7 @@ static int meson_vpu1_write_reg(u32 addr, u32 val)
 #endif
 }
 
-static int meson_vpu1_write_reg_bits(u32 addr, u32 val, u32 start, u32 len)
+int meson_vpu1_write_reg_bits(u32 addr, u32 val, u32 start, u32 len)
 {
 #ifdef CONFIG_AMLOGIC_MEDIA_RDMA
 	DRM_DEBUG("%s, 0x%x, 0x%x, %d, %d\n", __func__, addr, val, start, len);
@@ -194,7 +194,7 @@ static int meson_vpu2_write_reg(u32 addr, u32 val)
 #endif
 }
 
-static int meson_vpu2_write_reg_bits(u32 addr, u32 val, u32 start, u32 len)
+int meson_vpu2_write_reg_bits(u32 addr, u32 val, u32 start, u32 len)
 {
 #ifdef CONFIG_AMLOGIC_MEDIA_RDMA
 	return rdma_write_reg_bits(drm_vsync_rdma_handle[2], addr, val, start, len);

drivers/drm/meson_vpu_util.h

@@ -33,6 +33,8 @@ struct osd_scope_s {
 u32 meson_vpu_read_reg(u32 addr);
 int meson_vpu_write_reg(u32 addr, u32 val);
 int meson_vpu_write_reg_bits(u32 addr, u32 val, u32 start, u32 len);
+int meson_vpu1_write_reg_bits(u32 addr, u32 val, u32 start, u32 len);
+int meson_vpu2_write_reg_bits(u32 addr, u32 val, u32 start, u32 len);
 u32 meson_drm_read_reg(u32 addr);
 void meson_drm_write_reg(u32 addr, u32 val);
 void meson_drm_write_reg_bits(u32 addr, u32 val, u32 start, u32 len);

drivers/drm/vpu-hw/meson_osd_afbc.c

@@ -4,6 +4,11 @@
  */
 
 #include <linux/bitfield.h>
+
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+#include <linux/amlogic/media/vpu_secure/vpu_secure.h>
+#endif
+
 #include "meson_vpu_pipeline.h"
 #include "meson_vpu_reg.h"
 #include "meson_vpu_util.h"
@@ -472,6 +477,9 @@ static void g12a_osd_afbc_set_state(struct meson_vpu_block *vblk,
 	reverse_x = (plane_info->rotation & DRM_MODE_REFLECT_X) ? 1 : 0;
 	reverse_y = (plane_info->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0;
 
+	if (pipeline_state->sec_src)
+		pipeline_state->sec_src |= MALI_AFBCD_SECURE;
+
 	/* set osd path misc ctrl */
 	reg_ops->rdma_write_reg_bits(OSD_PATH_MISC_CTRL, 0x1,
 				(osd_index + 4), 1);
@@ -598,6 +606,9 @@ static void t7_osd_afbc_set_state(struct meson_vpu_block *vblk,
 			afbc_reg = &afbc->afbc_regs[osd_index];
 			plane_info = &mvps->plane_info[osd_index];
 
+			if (mvps->sec_src)
+				mvps->sec_src |= MALI_AFBCD_SECURE;
+
 			t7_osd_afbc_enable(vblk, reg_ops, afbc_stat_reg, osd_index, 1);
 
 			aligned_32 = 1;
@@ -773,6 +784,9 @@ static void t3_osd_afbc_set_state(struct meson_vpu_block *vblk,
 			afbc_reg = &afbc->afbc_regs[osd_index];
 			plane_info = &mvps->plane_info[osd_index];
 
+			if (mvps->sec_src)
+				mvps->sec_src |= MALI_AFBCD_SECURE;
+
 			t7_osd_afbc_enable(vblk, reg_ops, afbc_stat_reg, osd_index, 1);
 
 			aligned_32 = 1;

drivers/drm/vpu-hw/meson_vpu_osd_mif.c

@@ -15,6 +15,10 @@
 #ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT
 #include <linux/amlogic/media/amvecm/amvecm.h>
 #endif
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+#include <linux/amlogic/media/vpu_secure/vpu_secure.h>
+#endif
+
 #include "meson_vpu_pipeline.h"
 #include "meson_crtc.h"
 #include "meson_vpu_reg.h"
@@ -117,6 +121,8 @@ static struct osd_mif_reg_s osd_mif_reg[HW_OSD_MIF_NUM] = {
 
 static unsigned int osd_canvas[3][2];
 static u32 osd_canvas_index[3] = {0, 0, 0};
+static u32 osd_secure_input_index[] = {OSD1_INPUT_SECURE,
+	OSD2_INPUT_SECURE, OSD3_INPUT_SECURE};
 
 /*
  * Internal function to query information for a given format. See
@@ -649,6 +655,7 @@ static int osd_check_state(struct meson_vpu_block *vblk,
 	mvos->global_alpha = plane_info->global_alpha;
 	mvos->crtc_index = plane_info->crtc_index;
 	mvos->read_ports = plane_info->read_ports;
+	mvos->sec_en = plane_info->sec_en;
 
 	return 0;
 }
@@ -742,6 +749,7 @@ static void osd_set_state(struct meson_vpu_block *vblk,
 	struct meson_vpu_osd_state *mvos, *old_mvos = NULL;
 	struct meson_vpu_pipeline *pipe;
 	struct rdma_reg_ops *reg_ops;
+	struct meson_vpu_pipeline_state *mvps;
 	int crtc_index;
 	u32 pixel_format, canvas_index, src_h, byte_stride, flush_reg;
 	struct osd_scope_s scope_src = {0, 1919, 0, 1079};
@@ -762,6 +770,7 @@ static void osd_set_state(struct meson_vpu_block *vblk,
 	reg_ops = state->sub->reg_ops;
 	pipe = vblk->pipeline;
 	reg = osd->reg;
+	mvps = priv_to_pipeline_state(pipe->obj.state);
 	if (!reg) {
 		DRM_DEBUG("set_state break for NULL OSD mixer reg.\n");
 		return;
@@ -830,6 +839,9 @@ static void osd_set_state(struct meson_vpu_block *vblk,
 	else
 		osd_afbc_config(vblk, reg_ops, reg, vblk->index, afbc_en);
 
+	if (mvos->sec_en)
+		mvps->sec_src |= osd_secure_input_index[vblk->index];
+
 	osd_premult_enable(vblk, reg_ops, reg, alpha_div_en);
 	osd_global_alpha_set(vblk, reg_ops, reg, global_alpha);
 	osd_scan_mode_config(vblk, reg_ops, reg, pipe->subs[crtc_index].mode.flags &
@@ -937,6 +949,19 @@ static void osd_dump_register(struct meson_vpu_block *vblk,
 	seq_printf(seq, "%s_%-35s\t0x%08X\n", buff, "DIMM_CTRL:", value);
 }
 
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+static void osd_secure_cb(u32 arg)
+{
+	// TODO
+}
+#endif
+
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+	void *osd_secure_op[VPP_TOP_MAX] = {meson_vpu_write_reg_bits,
+					    meson_vpu1_write_reg_bits,
+					    meson_vpu2_write_reg_bits};
+#endif
+
 static void osd_hw_init(struct meson_vpu_block *vblk)
 {
 	struct meson_vpu_pipeline *pipeline;
@@ -959,6 +984,11 @@ static void osd_hw_init(struct meson_vpu_block *vblk)
 	osd->reg = &osd_mif_reg[vblk->index];
 	osd_ctrl_init(vblk, pipeline->subs[0].reg_ops, osd->reg);
 
+	/* osd secure function init */
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+	secure_register(OSD_MODULE, 0, osd_secure_op, osd_secure_cb);
+#endif
+
 	DRM_DEBUG("%s hw_init done.\n", osd->base.name);
 }
 

drivers/drm/vpu-hw/meson_vpu_postblend.c

@@ -14,6 +14,10 @@
 #include <linux/amlogic/media/video_sink/video.h>
 #endif
 
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+#include <linux/amlogic/media/vpu_secure/vpu_secure.h>
+#endif
+
 #include "meson_crtc.h"
 #include "meson_vpu_pipeline.h"
 #include "meson_vpu_util.h"
@@ -264,6 +268,10 @@ static void postblend_set_state(struct meson_vpu_block *vblk,
 	scope.v_start = 0;
 	scope.v_end = mvps->scaler_param[0].output_height - 1;
 
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+	secure_config(OSD_MODULE, mvps->sec_src, crtc_index);
+#endif
+
 	if (crtc_index == 0) {
 		vpp_osd1_blend_scope_set(vblk, reg_ops, reg, scope);
 
@@ -315,6 +323,10 @@ static void t7_postblend_set_state(struct meson_vpu_block *vblk,
 	scope.v_start = 0;
 	scope.v_end = mvps->scaler_param[0].output_height - 1;
 
+#ifdef CONFIG_AMLOGIC_MEDIA_SECURITY
+	secure_config(OSD_MODULE, mvps->sec_src, crtc_index);
+#endif
+
 	if (crtc_index == 0) {
 		vpp_osd1_blend_scope_set(vblk, reg_ops, reg, scope);
 

drivers/media/common/vpu_security/vpu_security.c

@@ -395,6 +395,7 @@ int secure_register(enum secure_module_e module,
 	pr_info("%s module=%d ok\n", __func__, module);
 	return 0;
 }
+EXPORT_SYMBOL(secure_register);
 
 int secure_unregister(enum secure_module_e module)
 {
@@ -437,6 +438,7 @@ int secure_config(enum secure_module_e module, int secure_src, u32 vpp_index)
 						    vpp_index);
 	return 0;
 }
+EXPORT_SYMBOL(secure_config);
 
 static ssize_t vpu_security_info_show(struct class *cla,
 				      struct class_attribute *attr, char *buf)