PD#SWPL-180321
Problem:
there are no usb pll and usb clock
Solution:
add usb pll and usb clock
Verify:
t6d br301
Change-Id: I24f381493a3f8d7d3510252fdc35ab2eb9b09b7e
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-180321
Problem:
it does not support amfc
Solution:
add amfc support
Verify:
t6d br301
Change-Id: Idb0d1d8aa3571402a636bd75018735fcb82bc489
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-180321
Problem:
there is no eth phy clock
Solution:
correct eth phy clock name
Verify:
t6d br301
Change-Id: Ie8ff90cf998c4a8064f01e4e52d63b7e284b4dd3
Signed-off-by: jian.hu <jian.hu@amlogic.com>
PD#SWPL-179629
Problem:
1 Optimize driver file formats using automated tools.
2 vpu_clk adds a flag feature to prevent glitch when operating the
clock.
3 The naming of hifi_pll is inconsistent with the clkid style.
4 The latest documentation provided by vlsi has changed the sys_clk
definition for USB and PCIe.
Solution:
1 Optimized
2 vpu_clk added flag CLK_OPS_PARENT_ENABLE.
3 The clkid of hifi_pll is named CLKID_HIFI_PLL.
4 USB and PCIe sys_clk have been updated.
Verify:
s6_bl201
Change-Id: I4560f7bc6d42583d4e62d184c182bfe199cb6955
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-174549
Problem:
secure permission needs to be set for the pwm_clk register
related to voltage regulation. Relevant clk configurations
need to be stored in bl31. kernel configurations need to
be deleted.
Solution:
fix it
Verify:
s7
Change-Id: If3477940b33f4a612743cb1c5c58ce45e59a8505
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-172965
Problem:
1 The mclk0 power supply uses the power supply inside the mclk_pll, so the
mclk0 output must ensure that mclk_pll is also enabled.
mclk_pll_clk can output clocks mclk_pll_src and fclk50m. The existence of
these two clock sources is meaningless.
2 If mclk0 uses mclk_pll as the clock source, div2 must be selected for
the clock of the later stage; otherwise, the output clock waveform of
mclk0 is abnormal.
Solution:
1 Delete the mclk_pll_src and fclk50m clock sources and set mclk_pll_clk
as the clock source of mclk0.
2 mclk0 selects div2 by default.
Verify:
s6_bl201
Change-Id: I9a8e3e1616b4c9b3b9c86990f86dc337f9f9c877
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-172965
Problem:
1 All I2C Masters (i2c_m_a-f) in a chip share an APB bus, which is
provided by sys_i2c_m_a. PWM is designed with a similar architecture, and
the APB bus of PWM is clock provided by sys_pwm_a.
2 The CLKID definition of smart card is inconsistent.
Solution:
1 The parent of sys_i2c_m_b-f is set to sys_i2c_m_a.
2 The parent of sys_pwm_b-i is set to sys_pwm_a.
3 CLKID_SC_DIV was renamed CLKID_SC.
Verify:
s6_bl201
Change-Id: I94482625f3a9fe387113edce21ed16e9dc63a074
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-172965
Problem:
1 mclk_pll and dspa_clk output are incorrect
2 mmc failed to insmod
3 Lost sys_i2c_s_a
Solution:
1 Update the table for mclk_pll
2 Update the parent table of the dspa
3 Ignore initializing gp0_pll
4 Added sys_i2c_s_a
Verify:
s6_bl201
Change-Id: I23586623d908ef871e178acf0da8883aabc12fc9
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-158289
Problem:
1 The register corresponding to oscin was updated;
2 Put some of the key clocks into bl31 for processing.
Solution:
fixed
Verify:
pxp
Change-Id: Ie5ea8b6c507ce136ba397e8e54362b72f05cf45c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-163105
Problem:
new earc Rx design
Solution:
changelist from https://scgit.amlogic.com/#/c/417153
1. new default setting for arc in
2. remove pll refresh when startup
3. when cmdc init, need refresh pll after pll default setting
4. force channel sync for channel mapping
5. add dmac bit29 check for common arc check
6. add iec raw channel status check
7. use chip info(arc_ch_sync/arc_in_new)
Verify:
use s7d
Change-Id: Id681334bfde57bfe71a870a16859e24712e262e3
Signed-off-by: qing.zhang <qing.zhang@amlogic.com>
PD#SWPL-158288
Problem:
1 Adding the logic associated with the en0p5 member makes the driver's
processing more complicated and messy.
2 Added clocks with security permissions.
Solution:
1 Only add CLK_MESON_PLL_FIXED_EN0P5 flag to implement the functions
of en0p5, so that the driver change cost is minimal.
2 Determine whether to add the CLK_MESON_PLL_FIXED_EN0P5 flag based
on whether en0p5 is enabled in init_regs.
3 Added scmi clocks
Verify:
pxp
Change-Id: I2f9e258569f4bed44cb5fd9b57368dbfa3c425cb
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-135780
Problem:
optimize clock performance.
Solution:
1 Optimize cpu_clk switching frequency timing;
2 Move all cpu_clk set frequency operations to bl31.
Verify:
pxp
Change-Id: I6147683b713a9b4854cd8f92e13b396f8705ea30
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-137984
Problem:
need specifies s7 clock name and CLKID
Solution:
fix it
Verify:
ptm
Change-Id: Ia9e3d126d275252ece4c76b6b98450d9c2707406
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-143601
Problem:
Need to bringup to console
Solution:
bringup to console for ab301
Verify:
tm2_ab301
Change-Id: I8f78a322da984eafa71ee21bee330eeccc224058
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
PD#SH-16937
Problem:
gen_clk is missing from the clock tree.
Solution:
added
Verify:
g12b
Change-Id: I66f2bd0b98ba0e4f05bb502ea72fe6b64ac45887
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-133117
Problem:
1 adapts to the new driver
2 some clock descriptions are incorrect
3 unified clock naming Convention
Solution:
fixed
Verify:
s1a_bg209
Change-Id: I4a7296a81b4662978b9aab225bf615ef4ec8747e
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-120773
Problem:
clock tree bringup for s1a
Solution:
add support
Verify:
pxp
Change-Id: I21040ed89cbd969bf71c250ef97b55592e4a43cb
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-130649
Problem:
there is no gp1 pll
Solution:
add gp1 support
Verify:
t3x
Change-Id: I47954709035c28e20079de481a960924e68d3629
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-128494
Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When c1 describes the same frequency, the corresponding
defined frequency is different.
Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz
Verify:
c1_ae400
Change-Id: Idec9a54d7010e18336be02fd488239dd7114986b
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#SWPL-124230
Problem:
1 fclk50m is not added to clock tree;
2 dsp clk failed to set the frequency;
3 clkid incorrectly defined.
Solution:
fixed
Verify:
c1_ae400
Change-Id: Ieef2f603f72a6b0104b295b37c4a9ec448923d7c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-121112
Problem:
clock tree bringup for c1
Solution:
support
Verify:
c1_ae400
Change-Id: Iaeacc52b6ac8266604614c2394d4a867e6edc203
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-125774
Problem:
there is no range driver on 32bit os
Solution:
support
Verify:
TXHD2 be319
Change-Id: Ie8e40ade1c577d62a5cb551a4b3b08dd9d6056ac
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-125774
Problem:
there is no dmux
Solution:
fix it
Verify:
TXHD2 be319
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
Change-Id: Idc946009ed96e9d718f191f2d6ec02b01a1e6894
PD#SWPL-118428
Problem:
there is no txhd2 clk driver
Solution:
need to support clk driver
Verify:
TXHD2 PXP
Change-Id: I15f13c03768185a36a6a0eb607ff3835eaacd5b0
Signed-off-by: junyi.zhao <junyi.zhao@amlogic.com>
PD#SWPL-118802
Problem:
1 not support non-secure ops function for cpu_cyn_clk
2 When each chip describes the same frequency, the corresponding
defined frequency is different.
Solution:
1 add non-secure ops function for cpu_cyn_clk
2 unify frequency to 666666666Hz
Verify:
all about board
Change-Id: Ia9fe27291ead5a56ed737c6f6aea97fbcddfd44f
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-117193
Problem:
t3x sys pll does not work well for dvfs
Solution:
add cpu and sys pll support
Verify:
t3x
Change-Id: Ia615b66b1ebd8c04b6d66679b73e6261615767f6
Signed-off-by: jian.hu <jian.hu@amlogic.com>
jian.hu