PD#SWPL-174974
Problem:
ldim require a hw interface dirspi_xfer to run in interrupt handle
Solution:
add a hw interface dirspi_xfer for ldim
Verify:
t5m ay301
Change-Id: I26e1a9890cc45ac0420d15ebea5e0a4bf2f18a56
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
PD#SWPL-168205
Problem:
lcevc data cannot be passed backward to vpp.
Solution:
add lcevc data path for pipeline.
Verify:
S7D
Change-Id: I656baa444025f4aaebfea67e19a011c152961c5f
Signed-off-by: zhenteng.tian <zhenteng.tian@amlogic.com>
PD#SWPL-176790
Problem:
S6: support read cali data
Solution:
S6: support read cali data
Verify:
S6 BL208
Change-Id: I3c3d7ba9f6b9ad619141ef0496b74c6648007d4a
Signed-off-by: Zhongfu Luo <zhongfu.luo@amlogic.com>
PD#SWPL-177015
Problem:
recovery mode ldim not work;
different mcu have different init times.
Solution:
add ini parameter to set
hw init on stable delay.
Verify:
t3x
Change-Id: Ia74161c5f541a84ed820e72a3a78e769b63a13e7
Signed-off-by: zijie.lin <zijie.lin@amlogic.com>
PD#SWPL-101847
Problem:
drm write registers to rdma table one by one, due to rdma table update
and rdma manager flush to real register are out of sync, so we want to
creat a fake table, the fake table will copy to rdma table after
pipeline register write done, and then config rdma vsync
Solution:
add rdma table for drm osd registers, and it can dynamic switching by
this node /sys/class/drm/card0/crtc0/rdma_table_switch.
echo 1 > /sys/class/drm/card0/crtc0/rdma_table_switch switch off
echo 0 > /sys/class/drm/card0/crtc0/rdma_table_switch switch on
Verify:
T3x s7 s5
Test:
DRM-OSD-33
Change-Id: I053daa7daaab672f8b1e9fc2c38a2d60552d6288
Signed-off-by: wenlong.zhang <wenlong.zhang@amlogic.com>
PD#SWPL-166466
Problem:
add rotation feature for T3
Solution:
add rotation feature for T3
Verify:
t3
Change-Id: I5865ff4843c3acdada755f1529fd0c41a0da972a
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-176775
Problem:
scatter keep size need expand for vdin
Solution:
scatter user can set scatter keep size
by register scatter owner.
Verify:
ohm
Change-Id: I4be8af6dff0454cda9191666ec48cd1e03464127
Signed-off-by: Hao Shi <hao.shi@amlogic.com>
PD#SWPL-168620
Problem:
when osd3 on/off, core2a and core2c reset, but lut
updated fail; drm enable osd3 is one vsync earlier
then dv core2c
Solution:
1.drm set core2c lut when osd3 off->on
2.add force_toggle_once debug
Verify:
s5
Test:
s5
Change-Id: I5fe2a7abd1f4b887da5f32a655a24418fee86b64
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#SWPL-176326
Problem:
s6 need to support 1080p120hz
Solution:
s6 need to support 1080p120hz
Verify:
S6
Test:
DRM-TX-130
Change-Id: I594f9671b36d3ea27c838bcf349a06cdcf2c707c
Signed-off-by: ruofei.zhao <ruofei.zhao@amlogic.com>
PD#SWPL-175926
Problem:
In DLG mode, display size is 3840x1080, aoi reg
is updated to 3840x1080, if disable/enable video
with no toggle, aoi reg will continue to be halved
Solution:
record the ori and updated AOI with new variables
Verify:
t5m
Change-Id: Idbc479a1d157fb35be131b7b9896e5cbf0ee3b67
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#SWPL-174021
Problem:
screen anomaly in dma_buf and vf frame data composition using composer.
Solution:
1.clear src_vf after completing the composition of a frame of data.
2.fix the issue vicp cannot perform compositing on dma_buf.
Verify:
T3X
Change-Id: Ibf5492d823a1f1e8540feae7d8e275487a83710c
Signed-off-by: zhenteng.tian <zhenteng.tian@amlogic.com>
PD#SWPL-172361
Problem:
bypass di according to compression ratio.
Solution:
Modify vc flow to implement this requirement.
Verify:
t5m
Change-Id: Iace3aec5f202369882793a42c66a6b590211cf29
Signed-off-by: qiyao.zhou <qiyao.zhou@amlogic.com>
PD#SWPL-175588
Problem:
Need support s7d revb
Solution:
1, add clk set for revb;
2, use clk interface for clk set
Verify:
S7D bm201
Change-Id: I168a942f6796208dd4dff67a13f065be14a40f0c
Signed-off-by: Tao Zeng <tao.zeng@amlogic.com>
PD#SWPL-160981
Problem:
The CQE v1 does not support placing tasks in memory
and does not support data encryption.
Solution:
support CQE v2
Verify:
S7 ax201
Change-Id: I0737d7b2b9e955838a9f3294d1f5faf5fd84aa17
Signed-off-by: Long <long.yu@amlogic.com>
PD#SWPL-168860
Problem:
add vpp afd info for hdmi and atv
Solution:
1. add vpp afd info for hdmi and atv
2. add crop info into afd input param
Verify:
t5m
Change-Id: I882a2d59c8738e3844d0ccc72e41a267a4463c62
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
PD#SWPL-168849
PD#SWPL-168856
Problem:
AFD feature development
Solution:
vdin pass afd info to vpp
Verify:
t5m
Change-Id: I3264ef109e560590b3da1c5ae0d2ab6355c8ea19
Signed-off-by: haitao.liu <haitao.liu@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-172344
Problem:
use video_composer to set the FRC working mode.
Solution:
use video_composer to set the FRC working mode.
Verify:
T5M
Change-Id: I70ad264105144ae07b2c8336e722c7369c025f74
Signed-off-by: zhenteng.tian <zhenteng.tian@amlogic.com>
PD#SWPL-172574
Problem:
Switch between horizontal and vertical screens crop error
Solution:
swap frame do not set crop when switch screen direction
Verify:
t7c
Change-Id: I3cc00d513e1b155af0674e2f21177e4217a4cc11
Signed-off-by: hai.cao <hai.cao@amlogic.com>
PD#SWPL-172429
Problem:
need optimize tcon multi data set flow
Solution:
optimize tcon multi data set flow
Verify:
ay301
Change-Id: I6ab7b24ea36d45108c911c1bee9ea1555f1eb573
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
PD#SWPL-170502
Problem:
During the switch to 444,8bit, drm will first set_nulldisp_vout_server,
and then disable hdmitx module. Since it is not currently hdmi_server,
callback send_drm_pkt cannot clear hdr pkt.
Solution:
Remove the is_cur_hdmi_mode judgment in the send_drm_pkt function,
and the hdr pkt can be cleared normally
Verify:
SC2
S5
Test:
DRM-TX-34，DRM-TX-78，DRM-TX-79，DRM-TX-80，DRM-TX-81
Change-Id: Ie85a6073c0c11a8100d344cefffecac613c82a22
Signed-off-by: ruofei.zhao <ruofei.zhao@amlogic.com>
PD#SWPL-172404
Problem:
need support new ctrl_type for demura multi lut
Solution:
add new ctrl_type for demura multi lut for resolution match
Verify:
ay301
Change-Id: If3cfdf49f65c31801b5014b2d5c268bc3521de9b
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
PD#SWPL-174291
Problem:
need to improve sido wifi performance.
Solution:
Switch sdio source clock to DIV2 to provide bandwidth
Verify:
S7 ax201
Change-Id: I471517743851f381ec5d50aac3df9b26e5fe4aee
Signed-off-by: Long <long.yu@amlogic.com>
jinbing.zhu