PD#SWPL-207769
Problem:
1. pm soc and pm use the same time
2. base:https://scgit.amlogic.com/#/c/501712
Solution:
1. keep the pm soc use for codecs
2. remove cache sync when save in user setting
Verify:
t5m
Change-Id: Iea9ad5ea0f295e06966190f112e353517986b499
Signed-off-by: qing.zhang <qing.zhang@amlogic.com>
(cherry picked from commit 12be0fd24f49ebedae9bcfd3be06f49d9c6b21ee)
PD#SWPL-212491
Problem:
need to switch between hdmi/cvbs output
when factory test
Solution:
add special flow to switch between CVBS/HDMI
Verify:
ohm/s7
Test:
fake plug
Change-Id: I6b14c3f6834fa96fcb6f15c558e2e5292526a9f2
Signed-off-by: zhou.han <zhou.han@amlogic.com>
(cherry picked from commit cbbca09fda4d3c6174e3e192e989cdc55e38b576)
PD#SWPL-198076
Problem:
pwm change to tee, not to be used
Solution:
use tee pwm
Verify:
s6
Change-Id: Ib8a49c4ce7887232b1215f0410ed5aaf5b6af0ea
Signed-off-by: jiabin.chen <jiabin.chen@amlogic.com>
(cherry picked from commit c4f93f5354fddc02479c7162e78d0291d5bb9c2e)
PD#SWPL-206124
Problem:
The box connects to a TV with "EDID Auto" support.
Right after bootup, the TV initially sends an EDID that
only supports SDR. This makes Weston set the hdr_priority
to 2 (SDR mode), and the driver saves this value to output SDR.
Later, when the TV detects the box supports HDCP 2.2,
it sends a new HDR-capable EDID through a plug event.
But here's the issue:
The driver first clears the HDR capability (hdr_priority=2)
after plugin. Then Weston tries to set hdr_priority to 1 (HDR mode)
Result: The HDR capability gets stuck and can't be restored."
Solution:
The driver always initializes all DV and HDR capabilities
first when entering hdr_strategy.
Verify:
ross
Test:
DRM-TX-143
Change-Id: If306788875a6f27ae249957fdb51e0a3bcc8fa40
Signed-off-by: zhou.han <zhou.han@amlogic.com>
PD#SWPL-213654
Problem:
Long time to display
Solution:
No delay added after checking hdcp
Verify:
t5w
Change-Id: Ia77db747ff8a31a3539ba38e4802e89644c5a858
Signed-off-by: Haotian Guo <haotian.guo@amlogic.com>
PD#SWPL-210247
Problem:
fix no signal after cor reset.
Solution:
set hpd low after cor reset.
Verify:
t5w
Change-Id: Icf260946192af9102a811425b2cf68a8930a12bc
Signed-off-by: yaoyu.xu <yaoyu.xu@amlogic.com>
PD#SWPL-202101
Problem:
kernel boot time is extended by tsensor probe calling sleep
Solution:
use delayed work to replace sleep call
Verify:
s6
Change-Id: I6cd69bfa3f5b425869f271f1386648b11fbecd4f
Signed-off-by: Liming Xue <liming.xue@amlogic.com>
PD#TV-159332
Problem:
pq xml by hdr type
Solution:
pq xml by hdr type
Verify:
Yocto
Change-Id: I765106b22c86359516b85d43be095765cecd285b
Signed-off-by: jianhua.yi <jianhua.yi@amlogic.com>
(cherry picked from commit c9f73279294dc8d9a511dab291122f7c71e9c56a)
PD#SWPL-207320
Problem:
When connecting to a TV that only supports game vrr, the upper layer
gets vrr_capable as 0, which triggers the QMS flow and results
in mode setting.
Solution:
add vrr_capable_type to divide qms and game.
Verify:
ross
Test:
DRM-TX-75
Change-Id: Ibebf3d70c34a894e14669f8a994f2ef7d11f3345
Signed-off-by: zhou.han <zhou.han@amlogic.com>
PD#SWPL-200485
PD#TV-157860
Problem:
video plane crop are miscalculated
Solution:
fix to calculate src width and height of video plane
Verify:
S7
Test:
DRM-OSD-69
Change-Id: Id6d96508e905b3694b41cb14aea349f5cc4fd663
Signed-off-by: linfang.zhao <linfang.zhao@amlogic.com>
PD#SWPL-210362
Problem:
dejaggy_en use different rdma table index for s6.
Solution:
change s6 dejaggy_en table index
Verify:
s905x5
Change-Id: Ibdc9842abc1aafff3ef5eabc4752b1355d96122d
Signed-off-by: qinghui.jiang <qinghui.jiang@amlogic.com>
PD#SWPL-209170
Problem:
add IOC Interface to replace direct module parameter access
Solution:
complete it
Verify:
t5m
Change-Id: I611d76f43af8c932788953f9a43788e8d29cd88a
Signed-off-by: Jian Cao <jian.cao@amlogic.com>
PD#SWPL-210177
PD#OTT-77737
Problem:
after hevcf clk setted rate, the loop is enabled/disabled, and
there is a probability that no output after clk is enabled
and check pass.
Solution:
after testing, it is found that it may be related to accuracy
of software delay 1ms, and delay of check is increased to 1.2ms
Verify:
s805x3
Change-Id: I733dd8dbdc6c4849fd3e39c87e34098d08bfe6fa
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>
PD#TV-157897
Problem:
di not support self-reverse when post write
Solution:
double check
Verify:
T6D
Change-Id: I96f9b3d1f6b4a5c0112e7a415fa93fb0a84f426e
Signed-off-by: rong.wang <rong.wang@amlogic.com>
PD#SWPL-204970
Problem:
MTN rdmif uses wrong op to config register when post-link mode
Solution:
use rdma op to config
Verify:
Verified on t6d
Change-Id: I4289a110f0ba781a58fd77fea0b7a6668de4c89f
Signed-off-by: brian.zhu <brian.zhu@amlogic.com>
PD#SWPL-201990
Problem:
When reverse case, inp_mif chroma y_start/end is wrong
Solution:
Correct the y_start/end value
Verify:
Verified on t6d
Change-Id: I151eabdd86cbd050edf24abffc3f3c5d0bff74ac
Signed-off-by: yufei.huan <yufei.huan@amlogic.com>
PD#SWPL-187820
PD#TV-157897
Problem:
pull down has wrong effect when in link mode
Solution:
remap blend mode with pulldown
Verify:
t6d
Change-Id: I1fa431cc6e0c2946148a5a65cf11b5b8c076d3ce
Signed-off-by: rong.wang <rong.wang@amlogic.com>
PD#SWPL-198169
PD#TV-157897
Problem:
When the screen is reversed, the video screen has a black bar
Solution:
fix di crop when di reverse
Verify:
txhd2
Change-Id: Id5c82b9bd13deb840678a8b0e0a2fb5cd42c98fb
Signed-off-by: brian.zhu <brian.zhu@amlogic.com>
PD#SWPL-207695
Problem:
not creating /dev/fb1 causes the boot animation not to show
Solution:
determine whether am_meson_create_drm_fbdev is requested for all osds
Verify:
s5
Test:
DRM-OSD-62
Change-Id: I8548e6dcf64af5bbcdb9665654af88edc8710904
Signed-off-by: mingyang.he <mingyang.he@amlogic.com>
PD#SWPL-208407
Problem:
t3 vpu clk being disabled when boot on
Solution:
remove unnecessary PARENT flag
customer should add CL 530892 manually
Verify:
t3 ar301
Change-Id: Icde712573bc241dd243b6c08c93595c8c304d72e
Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
(cherry picked from commit e4ffd5c866ec3e22242b87c78ba2f8d2e569f762)
PD#SWPL-194158
Problem:
enable hibernation for t3 linux
Solution:
modify logo_reserved in t3 linux dts
Verify:
t3
Test:
DRM-OSD-2
Change-Id: I8d2dc8aa64b6e9fb3088079ee14981e834349a4d
Signed-off-by: mingyang.he <mingyang.he@amlogic.com>
PD#SWPL-207716
Problem:
1 When the DI goes idle, the DI configures vpu_clkb to a lower
frequency (e.g., 18 MHz for S7/S7D/S6; 60 MHz for T3X/T5M, etc.).
2 The parent clock of vpu_clkb is defaulted to vpu_clk, which is
configured to a higher frequency (e.g., 666 MHz).
3 During early suspend, the VPU reduces vpu_clk to 25 MHz. As vpu_clkb
is a child clock of vpu_clk, it is also scaled down to a very low
frequency (e.g., (18 MHz / (666 MHz / 25 MHz)) ≈ 0.67 MHz).
4 When vpu_clkb drops to an extremely low frequency, it causes DI
register read/write exceptions, leading to a system bus hang.
Solution:
Allow modification of vpu_clkb_tmp configuration when setting vpu_clkb
frequency, effectively isolating vpu_clkb from vpu_clk frequency scaling
impacts.
Verify:
S905Y5/S905X5M/S905X5
Change-Id: If8527b98f849909f89f099d3efc5f121fc5447fe
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
PD#SWPL-208160
Problem:
dvb-t/t2 use top agc lead to unlock.
Solution:
switch dvb-t/t2 top agc to inner agc on T6D.
AMLDTVDEMOD_VER "V3.6.022".
Verify:
T6D.
Change-Id: I40e3f8713342f10ab0f03448d7646b94678c6c69
Signed-off-by: nengwen.chen <nengwen.chen@amlogic.com>
(cherry picked from commit 63deadc7b1a26f5a9aae98f7f482967229321c8f)
PD#SWPL-203367
PD#SWPL-175233
Problem:
low probability missing dvbt channel
Solution:
do reset when dvbt signal signal cannot be locked continuously
Verify:
BR30A1, AY301
Change-Id: I10e19021e020e8c2824eaf910a973c37d373be83
Signed-off-by: caiyi.xu <caiyi.xu@amlogic.com>
(cherry picked from commit b9e1ffc1e2a0fa15fb68e9aa1d8f016eb2b39901)
PD#SWPL-203475
Problem:
break is not triggered after timeout in kt/kl lock function
Solution:
return error after timeout
Verify:
sc2, s6
Change-Id: Id83f25825f19e367452c10828b37fba95ac0ffc7
Signed-off-by: Doosan Baek <doosan.baek@amlogic.com>
PD#SWPL-205751
Problem:
suspend and resume only need run once
Solution:
add status to control
Verify:
sc2
Change-Id: I947978b5fa55191feb3551460c4cd6dbd386ef19
Signed-off-by: hai.cao <hai.cao@amlogic.com>
(cherry picked from commit a67c4618e6822079c3170f4b03bbf9f44e209605)
PD#SWPL-200306
Problem:
can not access to hdmirx cor register due to the wrong clk_cntl
register
Solution:
Correct the address of clk_cntl
Verify:
T5W/TXHD2
Change-Id: I93a9fe92347bef155c60a5b177933abe59fd19c8
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-197815
Problem:
In current flow,we will turn off cfg clk but not turn off irq
in early suspend,clearing irq without cfg clk may causing panic,
as clearing irq need cfg clk enabled
Solution:
turn off irq when early suspend
Verify:
T6D
Change-Id: I02ad30bc452794ce7a97b9bd2505297a2eb21828
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
qing.zhang