rong.wang 014b19ff8b deinterlace: pull up vpu clkb when di reg [2/2]
PD#SWPL-189455

Problem:
di clk cannot pull up
when another channel doesn't exit normally

Solution:
modify reg flow code

Verify:
T3X/T5M

Change-Id: I002020b0a141df1a035bbd23803182780f532a54
Signed-off-by: rong.wang <rong.wang@amlogic.com>
2024-10-25 00:38:33 -07:00
2024-10-24 19:05:29 -07:00
2024-10-25 00:38:20 -07:00
2024-10-23 19:11:37 -07:00
2024-10-22 00:45:20 -07:00
S
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