Jian Hu 04fb2dd8d8 clk: optimize clock regmap interface [1/1]
PD#SWPL-134344

Problem:
t5d clk bringup

Solution:
optimize clock regmap interface

Verify:
t5d

Change-Id: Icff0c19a5d5251fcddce0c214d105a680197c5a9
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
2023-08-24 10:50:23 +08:00
2023-08-24 10:49:21 +08:00
S
Description
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118 MiB
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