Chuan Liu ee3ca92d7d clk: s6: Optimize clock driver [2/2] ...

PD#SWPL-158289

Problem:
1 The register corresponding to oscin was updated;
2 Put some of the key clocks into bl31 for processing.

Solution:
fixed

Verify:
pxp

Change-Id: Ie5ea8b6c507ce136ba397e8e54362b72f05cf45c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-07-13 19:04:51 +08:00

..

drm

hdmitx21: add vrr range and vic lists [1/1]

2024-06-27 20:10:21 +08:00

dt-bindings

clk: s6: Optimize clock driver [2/2]

2024-07-13 19:04:51 +08:00

linux/amlogic

s6: add codec_io/canvas/rdma support for s6 [1/1]

2024-07-13 18:59:02 +08:00

trace/events

amfc: add aml erofs ko to suppor hardware [1/2]

2024-07-04 10:52:19 +08:00

uapi/amlogic

media: h266 format define. [1/1]

2024-07-03 20:32:24 +08:00