Chuan Liu ee3ca92d7d clk: s6: Optimize clock driver [2/2] ...

PD#SWPL-158289

Problem:
1 The register corresponding to oscin was updated;
2 Put some of the key clocks into bl31 for processing.

Solution:
fixed

Verify:
pxp

Change-Id: Ie5ea8b6c507ce136ba397e8e54362b72f05cf45c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-07-13 19:04:51 +08:00

..

clock

clk: s6: Optimize clock driver [2/2]

2024-07-13 19:04:51 +08:00

display

bringup: Fixed s7d build error [1/1]

2024-04-18 18:59:09 +08:00

firmware

host driver: reconstruct dsp host driver [1/1]

2023-10-07 17:40:07 +08:00

gpio

pinctrl: s6: driver bringup [1/1]

2024-07-13 19:04:11 +08:00

hwspinlock

T3X: add hwspinlock. [3/3]

2023-05-18 21:08:38 +08:00

iio/adc

key: porting adc key driver [1/1]

2022-01-12 10:42:11 +08:00

input

ir: support 2 multi-format ir controller [1/1]

2024-04-18 19:00:18 +08:00

interrupt-controller

t3: bring up to console [1/1]

2022-09-07 20:06:44 +08:00

mailbox

mailbox: s6 mailbox pxp bringup [1/1]

2024-07-13 19:02:39 +08:00

power

S6: power domain: add config. [3/3]

2024-07-13 19:02:01 +08:00

pwm

typo: clear typo problem [1/1]

2022-09-07 20:06:45 +08:00

reset

reset: add reset controller support for s6 [1/1]

2024-07-13 18:58:44 +08:00