yao liu 2fdcd34205 amdv: t3x display abnormal [1/1] ...

PD#SWPL-199701

Problem:
1.For t3x,some registers require sequential writing,
with some bits written first and some bits written last,
so part tables cannot be used
2.Rdma write(clk reg) has not taken effect in next vsync because
rdma took too long.In this case, read value still 0x55, the next
write "or" operation will include 0x55 again.

Solution:
1.move t3x to original table;
2.remove "or" operation for clk reg.

Verify:
t3x

Change-Id: I89085f51c1cecc11ac866ee7bb1852152b5f3f0a
Signed-off-by: yao liu <yao.liu@amlogic.com>

2025-08-15 02:47:33 -07:00

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