Yu Tu 6704352fa8 pcie: Modified PLL flow to solve pll disconnect flow [1/1]
PD#SWPL-202074

Problem:
miss a patch lead to pcie boottime is different

Solution:
Synchronous patch

Verify:
bl201

Change-Id: Iaf957b71e9af83a1a625963bf298de0025e9bfbc
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
2025-02-18 05:56:54 -08:00
2025-02-13 22:11:20 -08:00
2024-11-13 19:24:25 -08:00
S
Description
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118 MiB
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