yiting.deng 79aecaf2f7 pll: s7: reset od when enable pll [1/1] ...

PD#SWPL-157952

Problem:
second enable pll will call set_rate, it reset od use init_regs
od bit, result pll rate changed

Solution:
store pll od when set_rate and rewrite it to regwith
other parm through enable

Verify:
s7_bh201

Change-Id: I04c236f3fd716fcf9b3ef1442eba8a5565dcdb02
Signed-off-by: yiting.deng <yiting.deng@amlogic.com>

2024-03-14 19:05:11 +08:00

android

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2024-02-19 20:47:24 +08:00

arch

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auto_patch

dvb-core: add support SYS_DVBC_ANNEX_B and C in dvbv3 [1/1]

2024-02-22 20:37:24 +08:00

drivers

pll: s7: reset od when enable pll [1/1]

2024-03-14 19:05:11 +08:00

include

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