Chuan Liu dfb83bfa5b clk: s6: Update the axi_clk register bits definition [1/1] ...

PD#SWPL-183185

Problem:
VLSI updated the axi_clk register bits definition in the document.

Solution:
Fixed

Verify:
s6_bl201

Change-Id: Ibb3e5f9c5a8d7cfce58932568f26ae3dc80e4c3c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-08-29 19:03:07 +08:00

..

drm

drm: optimize qms_brr_viclist function [1/1]

2024-08-27 16:38:21 +08:00

dt-bindings

clk: s6: Update the axi_clk register bits definition [1/1]

2024-08-29 19:03:07 +08:00

linux/amlogic

vc: notify frame display info to mediaproxy. [1/1]

2024-08-29 14:01:11 +08:00

trace/events

amfc: add aml erofs ko to suppor hardware [1/2]

2024-07-04 10:52:19 +08:00

uapi/amlogic

drm: optimize qms_brr_viclist function [1/1]

2024-08-27 16:38:21 +08:00